SAM9XE128 Atmel Corporation, SAM9XE128 Datasheet - Page 69
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SAM9XE128
Manufacturer Part Number
SAM9XE128
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9260.pdf
(290 pages)
2.SAM9261.pdf
(248 pages)
3.SAM9XE128.pdf
(860 pages)
4.SAM9XE128.pdf
(48 pages)
Specifications of SAM9XE128
Flash (kbytes)
128 Kbytes
Pin Count
217
Max. Operating Frequency
180 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
96
Ext Interrupts
96
Usb Transceiver
3
Usb Speed
Full Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
2
Uart
6
Ssc
1
Ethernet
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
Yes
Adc Channels
4
Adc Resolution (bits)
10
Adc Speed (ksps)
312
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
16
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.65 to 1.95
Fpu
No
Mpu / Mmu
No / Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- SAM9260 PDF datasheet
- SAM9261 PDF datasheet #2
- SAM9XE128 PDF datasheet #3
- SAM9XE128 PDF datasheet #4
- Current page: 69 of 290
- Download datasheet (5Mb)
2.9.12
ARM DDI 0165B
Exception priorities
When multiple exceptions arise at the same time, a fixed priority system determines the
order in which they are handled:
1.
2.
3.
4.
5.
6.
Some exceptions cannot occur together:
•
•
Data Abort.
FIQ.
Prefetch Abort.
Reset (highest priority).
IRQ.
BKPT, undefined instruction, and SWI (lowest priority).
The BKPT, or undefined instruction, and SWI exceptions are mutually exclusive.
Each corresponds to a particular (non-overlapping) decoding of the current
instruction.
When FIQs are enabled, and a Data Abort occurs at the same time as an FIQ, the
ARM9E-S enters the Data Abort handler, and proceeds immediately to the FIQ
vector.
A normal return from the FIQ causes the Data Abort handler to resume execution.
Data Aborts must have higher priority than FIQs to ensure that the transfer error
does not escape detection. You must add the time for this exception entry to the
worst-case FIQ latency calculations in a system that uses aborts to support virtual
memory.
The FIQ handler must not access any memory that can generate a Data Abort,
because the initial Data Abort exception condition is lost.
Copyright © 2000 ARM Limited. All rights reserved.
Programmer’s Model
2-27
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