SAM9XE128 Atmel Corporation, SAM9XE128 Datasheet - Page 121
SAM9XE128
Manufacturer Part Number
SAM9XE128
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9260.pdf
(290 pages)
2.SAM9261.pdf
(248 pages)
3.SAM9XE128.pdf
(860 pages)
4.SAM9XE128.pdf
(48 pages)
Specifications of SAM9XE128
Flash (kbytes)
128 Kbytes
Pin Count
217
Max. Operating Frequency
180 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
96
Ext Interrupts
96
Usb Transceiver
3
Usb Speed
Full Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
2
Uart
6
Ssc
1
Ethernet
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
Yes
Adc Channels
4
Adc Resolution (bits)
10
Adc Speed (ksps)
312
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
16
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.65 to 1.95
Fpu
No
Mpu / Mmu
No / Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- SAM9260 PDF datasheet
- SAM9261 PDF datasheet #2
- SAM9XE128 PDF datasheet #3
- SAM9XE128 PDF datasheet #4
- Current page: 121 of 290
- Download datasheet (5Mb)
ARM DDI 0165B
At the rising edge of CLK, if CLKEN is HIGH, and InMREQ is LOW, an instruction
fetch is taking place, and INSTR[31:0] contains the fetched instruction on the next
rising edge of the clock, when CLKEN is HIGH. This means that:
•
•
•
In all other cases, the ARM9E-S pipeline is stalled, and the coprocessor pipeline must
not advance.
Figure 6-2 shows the timing for these signals, and indicates when the coprocessor
pipeline must advance its state. In this timing diagram, Coproc clock shows the
effective clock applied to the pipeline follower in the coprocessor. It is derived such that
the coprocessor state must only advance on rising CLK edges when CLKEN is HIGH.
The method of implementing this is dependent on the design style used, such as clock
gating or register recirculating.
For efficient coprocessor design, an unmodified version of CLK must be applied to the
Execution stage of the coprocessor. This allows the coprocessor to continue executing
an instruction even when the ARM9E-S pipeline is stalled.
During the Execute stage, the condition codes are compared with the flags to determine
whether the instruction really executes or not. The output PASS is asserted (HIGH) if
the instruction in the Execute stage of the coprocessor pipeline:
•
•
the last instruction fetched must enter the Decode stage of the coprocessor
pipeline
the instruction in the Decode stage of the coprocessor pipeline must enter its
Execute stage
the fetched instruction must be sampled.
is a coprocessor instruction
has passed its condition codes.
Copyright © 2000 ARM Limited. All rights reserved.
Figure 6-2 ARM9E-S coprocessor clocking
ARM9E-S Coprocessor Interface
6-5
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