SAM9XE128 Atmel Corporation, SAM9XE128 Datasheet - Page 128
SAM9XE128
Manufacturer Part Number
SAM9XE128
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9260.pdf
(290 pages)
2.SAM9261.pdf
(248 pages)
3.SAM9XE128.pdf
(860 pages)
4.SAM9XE128.pdf
(48 pages)
Specifications of SAM9XE128
Flash (kbytes)
128 Kbytes
Pin Count
217
Max. Operating Frequency
180 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
96
Ext Interrupts
96
Usb Transceiver
3
Usb Speed
Full Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
2
Uart
6
Ssc
1
Ethernet
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
Yes
Adc Channels
4
Adc Resolution (bits)
10
Adc Speed (ksps)
312
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
16
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.65 to 1.95
Fpu
No
Mpu / Mmu
No / Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- SAM9260 PDF datasheet
- SAM9261 PDF datasheet #2
- SAM9XE128 PDF datasheet #3
- SAM9XE128 PDF datasheet #4
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- Download datasheet (5Mb)
ARM9E-S Coprocessor Interface
6.5
6-12
Interlocked MCR
ARM processor pipeline
LATECANCEL
WDATA[31:0]
RDATA[31:0]
INSTR[31:0]
CHSD[1:0]
CHSE[1:0]
InMREQ
(MCR)
(MRC)
PASS
CLK
the Decode stage of the coprocessor pipeline, and remains there until it can enter the
Execute stage.
Figure 6-5 gives an example of an interlocked MCR.
If the data for an
first Decode cycle, the ARM9E-S pipeline interlocks for one or more cycles until the
data is available. An example of this is where the register being transferred is the
destination from a preceding
Copyright © 2000 ARM Limited. All rights reserved.
MCR
operation is not available inside the ARM9E-S pipeline during its
LDR
instruction. In this situation the
Figure 6-5 ARM9E-S interlocked MCR
MCR
instruction enters
ARM DDI 0165B
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