SAM9XE128 Atmel Corporation, SAM9XE128 Datasheet - Page 237
SAM9XE128
Manufacturer Part Number
SAM9XE128
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9260.pdf
(290 pages)
2.SAM9261.pdf
(248 pages)
3.SAM9XE128.pdf
(860 pages)
4.SAM9XE128.pdf
(48 pages)
Specifications of SAM9XE128
Flash (kbytes)
128 Kbytes
Pin Count
217
Max. Operating Frequency
180 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
96
Ext Interrupts
96
Usb Transceiver
3
Usb Speed
Full Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
2
Uart
6
Ssc
1
Ethernet
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
Yes
Adc Channels
4
Adc Resolution (bits)
10
Adc Speed (ksps)
312
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
16
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.65 to 1.95
Fpu
No
Mpu / Mmu
No / Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- SAM9260 PDF datasheet
- SAM9261 PDF datasheet #2
- SAM9XE128 PDF datasheet #3
- SAM9XE128 PDF datasheet #4
- Current page: 237 of 290
- Download datasheet (5Mb)
B.4
B.4.1
B.4.2
B.4.3
ARM DDI 0165B
ARM9E-S design considerations
Master clock
JTAG interface timing
Interrupt timing
When an ARM9TDMI hard macrocell design is being converted to ARM9E-S, the
following areas require special consideration:
•
•
•
•
•
The master clock to the ARM9E-S, CLK, is inverted with respect to GCLK used on
the ARM9TDMI hard macrocell. The rising edge of the clock is the active edge of the
clock, on which all inputs are sampled.
All outputs are generated safely from the rising edge of CLK, with the following
exceptions:
CORECLKENOUT
DBGTDO
All JTAG signals on the ARM9E-S are synchronous to the master clock input, CLK.
When an external TCK is used, use an external synchronizer to the ARM9E-S.
As with all ARM9E-S signals, the interrupt signals, nIRQ and nFIQ, are sampled on
the rising edge of CLK.
When you are converting an ARM9TDMI hard macrocell design where the ISYNC
signal is asserted LOW, add a synchronizer to the design to synchronize the interrupt
signals before they are applied to the ARM9E-S.
Master clock
JTAG interface timing
Interrupt timing
Address class signal timing on page B-8
Data Aborts on page B-8.
Copyright © 2000 ARM Limited. All rights reserved.
This signal can change from the rising edge of CLK and has a
causal relationship with CLKEN.
This signal can change from the rising edge of CLK and has a
causal relationship with DBGSDOUT.
Differences Between the ARM9E-S and the ARM9TDMI
B-7
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