SAM9XE128 Atmel Corporation, SAM9XE128 Datasheet - Page 273
SAM9XE128
Manufacturer Part Number
SAM9XE128
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9260.pdf
(290 pages)
2.SAM9261.pdf
(248 pages)
3.SAM9XE128.pdf
(860 pages)
4.SAM9XE128.pdf
(48 pages)
Specifications of SAM9XE128
Flash (kbytes)
128 Kbytes
Pin Count
217
Max. Operating Frequency
180 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
96
Ext Interrupts
96
Usb Transceiver
3
Usb Speed
Full Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
2
Uart
6
Ssc
1
Ethernet
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
Yes
Adc Channels
4
Adc Resolution (bits)
10
Adc Speed (ksps)
312
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
16
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.65 to 1.95
Fpu
No
Mpu / Mmu
No / Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- SAM9260 PDF datasheet
- SAM9261 PDF datasheet #2
- SAM9XE128 PDF datasheet #3
- SAM9XE128 PDF datasheet #4
- Current page: 273 of 290
- Download datasheet (5Mb)
ARM DDI 0165B
Instruction comparison bit functions are described in Table C-6.
.
Bit
number
1
4
5
6
7
8
Table C-6 Watchpoint control register for instruction comparison functions
Copyright © 2000 ARM Limited. All rights reserved.
Name
ITBIT
InTRANS
DBGEXT
CHAIN
RANGE
ENABLE
Function
Compares against the Thumb state signal from the core to
determine between a Thumb (ITBIT = 1) instruction fetch or an
ARM (ITBIT = 0) instruction fetch.
Compares against the not translate signal from the core in order to
determine between a user mode (InTRANS = 0) instruction fetch,
and a privileged mode (InTRANS = 1) fetch.
Is an external input into the EmbeddedICE-RT logic that allows
the watchpoint to be dependent upon some external condition.
The DBGEXT input for watchpoint 0 is labelled DBGEXT[0],
and the DBGEXT input for watchpoint 1 is labeled DBGEXT[1].
Selects the chain output of another watchpoint unit in order to
implement some debugger requests. For example, breakpoint on
address YYY only when in process XXX.
In the ARM9E-S EmbeddedICE-RT logic, the CHAINOUT
output of watchpoint 1 is connected to the CHAIN input of
watchpoint 0. The CHAINOUT output is derived from a latch.
The address or control field comparator drives the write enable for
the latch, and the input to the latch is the value of the data field
comparator. The CHAINOUT latch is cleared when the control
value register is written, or when nTRST is LOW.
Can be connected to the range output of another watchpoint
register. In the ARM9E-S EmbeddedICE-RT logic, the address
comparator output of watchpoint 1 is connected to the RANGE
input of watchpoint 0. This allows you to couple two watchpoints
for detecting conditions that occur simultaneously, for example,
for range-checking.
If a watchpoint match occurs, the internal IBREAKPTsignal is
only asserted when the ENABLE bit is set. This bit only exists in
the value register, it cannot be masked.
Debug in depth
C-33
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