SAM4S16C Atmel Corporation, SAM4S16C Datasheet - Page 83
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SAM4S16C
Manufacturer Part Number
SAM4S16C
Description
Manufacturer
Atmel Corporation
Specifications of SAM4S16C
Flash (kbytes)
1024 Kbytes
Pin Count
100
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
79
Ext Interrupts
79
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
2
Uart
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
1000
Analog Comparators
1
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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11.6.3
11.6.3.1
11.6.3.2
11100A–ATARM–28-Oct-11
11100A–ATARM–28-Oct-11
Instruction Descriptions
Operands
Restrictions when Using PC or SP
Table 11-14. CMSIS Functions to Generate some Cortex-M4 Instructions (Continued)
The CMSIS also provides a number of functions for accessing the special registers using MRS
and MSR instructions:
Table 11-15. CMSIS Intrinsic Functions to Access the Special Registers
An instruction operand can be an ARM register, a constant, or another instruction-specific
parameter. Instructions act on the operands and often store the result in a destination register.
When there is a destination register in the instruction, it is usually specified before the operands.
Operands in some instructions are flexible, can either be a register or a constant. See
Second Operand”
Many instructions have restrictions on whether the Program Counter (PC) or Stack Pointer (SP)
for the operands or destination register can be used. See instruction descriptions for more
information.
Note:
Instruction
REVSH
RBIT
SEV
WFE
WFI
Special Register
PRIMASK
FAULTMASK
BASEPRI
CONTROL
MSP
PSP
Bit[0] of any address written to the PC with a BX, BLX, LDM, LDR, or POP instruction must be 1
for correct execution, because this bit indicates the required instruction set, and the Cortex-M4
processor only supports Thumb instructions.
.
Access
Read
Write
Read
Write
Read
Write
Read
Write
Read
Write
Read
Write
CMSIS Function
uint32_t __REVSH(uint32_t int value)
uint32_t __RBIT(uint32_t int value)
void __SEV(void)
void __WFE(void)
void __WFI(void)
CMSIS Function
uint32_t __get_PRIMASK (void)
void __set_PRIMASK (uint32_t value)
uint32_t __get_FAULTMASK (void)
void __set_FAULTMASK (uint32_t value)
uint32_t __get_BASEPRI (void)
void __set_BASEPRI (uint32_t value)
uint32_t __get_CONTROL (void)
void __set_CONTROL (uint32_t value)
uint32_t __get_MSP (void)
void __set_MSP (uint32_t TopOfMainStack)
uint32_t __get_PSP (void)
void __set_PSP (uint32_t TopOfProcStack)
SAM4S
SAM4S
“Flexible
83
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