SAM4S16C Atmel Corporation, SAM4S16C Datasheet - Page 199

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SAM4S16C

Manufacturer Part Number
SAM4S16C
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM4S16C

Flash (kbytes)
1024 Kbytes
Pin Count
100
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
79
Ext Interrupts
79
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
2
Uart
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
1000
Analog Comparators
1
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
11100A–ATARM–28-Oct-11
11100A–ATARM–28-Oct-11
The CMSIS provides thread-safe code that gives atomic access to the Interrupt Priority Regis-
ters.
and corresponding CMSIS variables that have one bit per interrupt.
Table 11-29. Mapping of interrupts to the interrupt variables
1.
Interrupts
0-34
35-63
• the 4-bit fields of the Interrupt Priority Registers map to an array of 4-bit integers, so that the
array IP[0] to IP[34] corresponds to the registers IPR0-IPR8, and the array entry IP[n] holds
the interrupt priority for interrupt n.
Table 11-29
Each array element corresponds to a single NVIC register, for example the element
ICER[0] corresponds to the ICER0 register.
CMSIS array elements
Set-enable
ISER[0]
ISER[1]
shows how the interrupts, or IRQ numbers, map onto the interrupt registers
Clear-enable
ICER[0]
ICER[1]
(1)
Set-pending
ISPR[0]
ISPR[1]
Clear-pending
ICPR[0]
ICPR[1]
IABR[0]
IABR[1]
Active Bit
SAM4S
SAM4S
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