SAM4S16C Atmel Corporation, SAM4S16C Datasheet - Page 399
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SAM4S16C
Manufacturer Part Number
SAM4S16C
Description
Manufacturer
Atmel Corporation
Specifications of SAM4S16C
Flash (kbytes)
1024 Kbytes
Pin Count
100
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
79
Ext Interrupts
79
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
2
Uart
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
1000
Analog Comparators
1
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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23. Bus Matrix (MATRIX)
23.1
23.2
23.2.1
23.2.2
11100A–ATARM–28-Oct-11
11100A–ATARM–28-Oct-11
Description
Embedded Characteristics
Matrix Masters
Matrix Slaves
The Bus Matrix implements a multi-layer AHB that enables parallel access paths between multi-
ple AHB masters and slaves in a system, which increases the overall bandwidth. Bus Matrix
interconnects 4 AHB Masters to 5 AHB Slaves. The normal latency to connect a master to a
slave is one cycle except for the default master of the accessed slave which is connected
directly (zero cycle latency).
The Bus Matrix user interface also provides a Chip Configuration User Interface with Registers
that allow to support application specific features.
The Bus Matrix manages 4 masters, which means that each master can perform an access con-
currently with others, to an available slave.
Each master has its own decoder, which is defined specifically for each master. In order to sim-
plify the addressing, all the masters have the same decodings.
Table 23-1.
The Bus Matrix manages 5 slaves. Each slave has its own arbiter, allowing a different arbitration
per slave.
Table 23-2.
Master 0
Master 1
Master 2
Master 3
Slave 0
Slave 1
Slave 2
Slave 3
Slave 4
List of Bus Matrix Masters
List of Bus Matrix Slaves
Internal SRAM
Internal ROM
Internal Flash
External Bus Interface
Peripheral Bridge
Cortex-M4 Instruction/Data
Cortex-M4 System
Peripheral DMA Controller (PDC)
CRC Calculation Unit
SAM4S
SAM4S
399
399
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