SAM4S16C Atmel Corporation, SAM4S16C Datasheet - Page 253
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SAM4S16C
Manufacturer Part Number
SAM4S16C
Description
Manufacturer
Atmel Corporation
Specifications of SAM4S16C
Flash (kbytes)
1024 Kbytes
Pin Count
100
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
79
Ext Interrupts
79
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
2
Uart
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
1000
Analog Comparators
1
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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Condition field
Conditional execution
Context
Coprocessor
Debugger
Direct Memory Access
(DMA)
Doubleword
Doubleword-aligned
Endianness
Exception
Exception service routine
Exception vector
Flat address mapping
A four-bit field in an instruction that specifies a condition under which the instruction can execute.
If the condition code flags indicate that the corresponding condition is true when the instruction starts
executing, it executes normally. Otherwise, the instruction does nothing.
The environment that each process operates in for a multitasking operating system. In ARM
processors, this is limited to mean the physical address range that it can access in memory and the
associated memory access permissions.
A processor that supplements the main processor. Cortex-M4 does not support any coprocessors.
A debugging system that includes a program, used to detect, locate, and correct software faults,
together with custom hardware that supports software debugging.
An operation that accesses main memory directly, without the processor performing any accesses to
the data concerned.
A 64-bit data item. The contents are taken as being an unsigned integer unless otherwise stated.
Byte ordering. The scheme that determines the order that successive bytes of a data word are stored
in memory. An aspect of the system’s memory mapping.
See also
An event that interrupts program execution. When an exception occurs, the processor suspends the
normal program flow and starts execution at the address indicated by the corresponding exception
vector. The indicated address contains the first instruction of the handler for the exception.
An exception can be an interrupt request, a fault, or a software-generated system exception. Faults
include attempting an invalid memory access, attempting to execute an instruction in an invalid
processor state, and attempting to execute an undefined instruction.
See
See
A system of organizing memory in which each physical address in the memory space is the same as
the corresponding virtual address.
A data item having a memory address that is divisible by eight.
“Interrupt handler”
“Interrupt vector”
“Little-endian (LE)”
.
.
and
“Big-endian (BE)”
SAM4S
SAM4S
253
253
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