SAM4S16C Atmel Corporation, SAM4S16C Datasheet - Page 144
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SAM4S16C
Manufacturer Part Number
SAM4S16C
Description
Manufacturer
Atmel Corporation
Specifications of SAM4S16C
Flash (kbytes)
1024 Kbytes
Pin Count
100
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
79
Ext Interrupts
79
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
2
Uart
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
1000
Analog Comparators
1
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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11.6.6.6
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SAM4S
SAM4S
SMLSD and SMLSLD
Signed Multiply Subtract Dual and Signed Multiply Subtract Long Dual
Syntax
op{X}{cond} Rd, Rn, Rm, Ra
where:
op
cond
Rd
Rn, Rm
Ra
Operation
The
halfwords. This instruction:
The
This instruction:
Restrictions
In these instructions:
Condition Flags
This instruction sets the Q flag if the accumulate operation overflows. Overflow cannot occur
during the multiplications or subtraction.
For the Thumb instruction set, these instructions do not affect the condition code flags.
Examples
• Optionally rotates the halfwords of the second operand.
• Performs two signed 16 × 16-bit halfword multiplications.
• Subtracts the result of the upper halfword multiplication from the result of the lower halfword
• Adds the signed accumulate value to the result of the subtraction.
• Writes the result of the addition to the destination register.
• Optionally rotates the halfwords of the second operand.
• Performs two signed 16 × 16-bit halfword multiplications.
• Subtracts the result of the upper halfword multiplication from the result of the lower halfword
• Adds the 64-bit value in
• Writes the 64-bit result of the addition to the
• Do not use SP and do not use PC.
multiplication.
multiplication.
SMLSLD
SMLSD
instruction interprets the values from the first and second operands as four signed
instruction interprets the values from
is one of:
SMLSD
SMLSDX
SMLSLD
SMLSLDX
If
If the
is an optional condition code, see
is the destination register.
are registers holding the first and second operands.
is the register holding the accumulate value.
X
is present, the multiplications are bottom × top and top × bottom.
X
Signed Multiply Subtract Dual.
is omitted, the multiplications are bottom × bottom and top × top.
Signed Multiply Subtract Long Dual.
Signed Multiply Subtract Dual Reversed
Signed Multiply Subtract Long Dual Reversed.
RdHi
and
RdLo
to the result of the subtraction.
“Conditional Execution”
RdHi
Rn
and
and
Rm
RdLo
as four signed halfwords.
.
.
11100A–ATARM–28-Oct-11
11100A–ATARM–28-Oct-11
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