SAM4S16C Atmel Corporation, SAM4S16C Datasheet - Page 125
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SAM4S16C
Manufacturer Part Number
SAM4S16C
Description
Manufacturer
Atmel Corporation
Specifications of SAM4S16C
Flash (kbytes)
1024 Kbytes
Pin Count
100
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
79
Ext Interrupts
79
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
2
Uart
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
1000
Analog Comparators
1
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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11.6.5.15
11.6.5.16
11100A–ATARM–28-Oct-11
11100A–ATARM–28-Oct-11
UADD16 and UADD8
TST and TEQ
Test bits and Test Equivalence.
Syntax
TST{cond} Rn, Operand2
TEQ{cond} Rn, Operand2
where:
cond
Rn
Operand2
Operation
These instructions test the value in a register against
based on the result, but do not write the result to a register.
The
This is the same as the
To test whether a bit of
bit set to 1 and all other bits cleared to 0.
The
of
Use the
TEQ
Exclusive OR of the sign bits of the two operands.
Restrictions
Do not use SP and do not use PC
Condition Flags
These instructions:
Examples
Unsigned Add 16 and Unsigned Add 8
Syntax
op{cond}{Rd,} Rn, Rm
• update the N and Z flags according to the result
• can update the C flag during the calculation of
• do not affect the V flag.
Operand2
TST
TEQEQ R10, R9 ; Conditionally test if value in R10 is equal to
is also useful for testing the sign of a value. After the comparison, the N flag is the logical
TST
TEQ
instruction performs a bitwise AND operation on the value in
TEQ
instruction performs a bitwise Exclusive OR operation on the value in
. This is the same as the
R0, #0x3F8 ; Perform bitwise AND of R0 value to 0x3F8,
instruction to test if two values are equal without affecting the V or C flags.
is an optional condition code, see
is the register holding the first operand.
is a flexible second operand. See
; APSR is updated but result is discarded
; value in R9, APSR is updated but result is discarded.
Rn
ANDS
is 0 or 1, use the
instruction, except that it discards the result.
.
EORS
instruction, except that it discards the result.
TST
“Flexible Second Operand”
“Conditional Execution”
instruction with an
Operand2
Operand2
, see
. They update the condition flags
“Flexible Second Operand”
Operand2
.
Rn
for details of the options.
and the value of
constant that has that
Rn
SAM4S
SAM4S
and the value
Operand2
125
125
.
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