ATxmega64B3 Atmel Corporation, ATxmega64B3 Datasheet - Page 60

• Manufacturer Part Number: ATxmega64B3
• Manufacturer: Atmel Corporation

Specifications of ATxmega64B3

• Flash (kbytes): 64 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 36
• Ext Interrupts: 36
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 2
• Twi (i2c): 1
• Uart: 1
• Segment Lcd: 100
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 2
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

5.14.4
8291A–AVR–10/11
TRIGSRC – Trigger Source Register
Table 5-8.
• Bit 7:0 – TRIGSRC[7:0]: Trigger Source Select
These bits select which trigger source is used for triggering a transfer on the DMA channel. A
zero value means that the trigger source is disabled. For each trigger source, the value to put in
the TRIGSRC register is the sum of the module’s or peripheral’s base value and the offset value
for the trigger source in the module or peripheral.
all modules and peripherals.
value for the trigger sources in the different modules and peripheral types. For modules or
peripherals which do not exist for a device, the transfer trigger does not exist. Refer to the device
datasheet for the list of peripherals available.
If the interrupt flag related to the trigger source is cleared or the interrupt level enabled so that an
interrupt is triggered, the DMA request will be lost. Since a DMA request can clear the interrupt
flag, interrupts can be lost.
Note:
Table 5-9.
Bit
+0x03
Read/Write
Initial Value
TRIGSRC Base Value
DESTDIR[1:0]
For most trigger sources the request is cleared by accessing a register belonging to the peripheral
with the request. Refer to the different peripheral chapters for how requests are generated and
cleared.
00
01
10
11
0x4A
0x00
0x01
0x04
0x10
0x20
0x40
0x46
R/W
DMA channel destination address mode settings.
DMA trigger source base values for all modules and peripherals.
7
0
Group Configuration
R/W
6
0
Group Configuration
Table 5-10 on page 61
FIXED
DEC
INC
R/W
-
5
0
ADCA
ADCB
TCC0
TCC1
SPIC
OFF
SYS
AES
R/W
4
0
TRIGSRC[7:0]
Description
Fixed
Increment
Decrement
Reserved
Table 5-9 on page 60
Description
Software triggers only
Event system DMA triggers base value
AES DMA trigger value
ADCA DMA triggers base value
ADCB DMA triggers base value
Timer/counter C0 DMA triggers base value
Timer/counter C1 triggers base value
SPI C DMA triggers value
R/W
3
0
to
Atmel AVR XMEGA B
Table 5-13 on page 61
R/W
2
0
R/W
1
0
shows the base value for
R/W
shows the offset
0
0
TRIGSRC
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