ATxmega64B3 Atmel Corporation, ATxmega64B3 Datasheet - Page 193

• Manufacturer Part Number: ATxmega64B3
• Manufacturer: Atmel Corporation

Specifications of ATxmega64B3

• Flash (kbytes): 64 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 36
• Ext Interrupts: 36
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 2
• Twi (i2c): 1
• Uart: 1
• Segment Lcd: 100
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 2
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

15.6
15.6.1
8291A–AVR–10/11
Fault Protection
Fault Actions
cations. A block diagram of the pattern generator is shown in
on page
put the waveform from CCA.
Figure 15-5. Pattern generator block diagram.
As with the other timer/counter double buffered registers, the register update is synchronized to
the UPDATE condition set by the waveform generation mode. If the synchronization provided is
not required by the application, the application code can simply access the DTIOE and PORTx
registers directly.
The pin directions must be set for any output from the pattern generator to be visible on the port.
The fault protection feature enables fast and deterministic action when a fault is detected. The
fault protection is event controlled. Thus, any event from the event system can be used to trigger
a fault action, such as over-current indication from analog comparator or ADC measurements.
When fault protection is enabled, an incoming event from any of the selected event channels
can trigger the event action. Each event channel can be separately enabled as a fault protection
input, and the specified event channels will be ORed together, allowing multiple event sources to
be used for fault protection at the same time.
When a fault is detected, the direction clear action will clear the direction (DIR) register in the
associated port, setting all port pins as tri-stated inputs.
The fault detection flag is set, the timer/counter’s error interrupt flag is set, and the optional inter-
rupt is generated.
There is maximum of two peripheral clock cycles from when an event occurs in a peripheral until
the fault protection triggers the event action. Fault protection is fully independent of the CPU and
DMA, but requires the peripheral clock to run.
UPDATE
193. For each port pin where the corresponding OOE bit is set, the multiplexer will out-
BV
EN
OUTOVEN
DTLSBUF
Timer/Counter 0 (TCx0)
BV
EN
Atmel AVR XMEGA B
DTHSBUF
OUTx
”Pattern generator block diagram.”
Px[7:0]
CCA WG output
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