ATxmega64B3 Atmel Corporation, ATxmega64B3 Datasheet - Page 267

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ATxmega64B3

Manufacturer Part Number
ATxmega64B3
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of ATxmega64B3

Flash (kbytes)
64 Kbytes
Pin Count
64
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
36
Ext Interrupts
36
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
2
Twi (i2c)
1
Uart
1
Segment Lcd
100
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
2
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
AES/DES
Sram (kbytes)
4
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
2
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATxmega64B3-AU
Manufacturer:
Atmel
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Part Number:
ATxmega64B3-AUR
Manufacturer:
Atmel
Quantity:
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20.7.4
20.8
20.9
Table 20-4.
8291A–AVR–10/11
Address
+0x00
+0x01
+0x02
+0x03
Offset
0x00
Register Summary
Interrupt vector Summary
DATA – Data register
Name
SPI interrupt vector and its offset word address.
INTCTRL
STATUS
CTRL
DATA
SPI_vect
• Bit 6 – WRCOL: Write Collision Flag
The WRCOL flag is set if the DATA register is written during a data transfer. This flag is cleared
by first reading the STATUS register when WRCOL is set, and then accessing the DATA
register.
• Bit 5:0 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
The DATA register is used for sending and receiving data. Writing to the register initiates the
data transmission, and the byte written to the register will be shifted out on the SPI output line.
Reading the register causes the shift register receive buffer to be read, returning the last byte
successfully received.
Source
CLK2X
Bit 7
Bit
+0x03
Read/Write
Initial Value
IF
ENABLE
WRCOL
Bit 6
R/W
7
0
Interrupt Description
SPI interrupt vector
R/W
Bit 5
DORD
6
0
R/W
MASTER
5
0
Bit 4
DATA[7:0]
R/W
4
0
Bit 3
DATA[7:0]
MODE[1:0]
R/W
3
0
Atmel AVR XMEGA B
Bit 2
R/W
2
0
Bit 1
PRESCALER[1:0]
INTLVL[1:0]
R/W
1
0
Bit 0
R/W
0
0
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