ATxmega64B3 Atmel Corporation, ATxmega64B3 Datasheet - Page 246

• Manufacturer Part Number: ATxmega64B3
• Manufacturer: Atmel Corporation

Specifications of ATxmega64B3

• Flash (kbytes): 64 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 36
• Ext Interrupts: 36
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 2
• Twi (i2c): 1
• Uart: 1
• Segment Lcd: 100
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 2
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

19.5.1.2
19.5.1.3
19.5.1.4
19.5.2
19.5.3
19.6
8291A–AVR–10/11
TWI Slave Operation
Transmitting Data Packets
Receiving Data Packets
Case M2: Address packet transmit complete - Address not acknowledged by slave
Case M3: Address packet transmit complete - Direction bit cleared
Case M4: Address packet transmit complete - Direction bit set
If no slave device responds to the address, the master write interrupt flag and the master
received acknowledge flag are set. The clock hold is active at this point, preventing further activ-
ity on the bus.
If the master receives an ACK from the slave, the master write interrupt flag is set and the mas-
ter received acknowledge flag is cleared. The clock hold is active at this point, preventing further
activity on the bus.
If the master receives an ACK from the slave, the master proceeds to receive the next byte of
data from the slave. When the first data byte is received, the master read interrupt flag is set and
the master received acknowledge flag is cleared. The clock hold is active at this point, prevent-
ing further activity on the bus.
Assuming case M3 above, the master can start transmitting data by writing to the master data
register. If the transfer was successful, the slave will signal with ACK. The master write interrupt
flag is set, the master received acknowledge flag is cleared, and the master can prepare new
data to send. During data transfer, the master is continuously monitoring the bus for collisions.
The received acknowledge flag must be checked by software for each data packet transmitted
before the next data packet can be transferred. The master is not allowed to continue transmit-
ting data if the slave signals a NACK.
If a collision is detected and the master loses arbitration during transfer, the arbitration lost flag is
set.
Assuming case M4 above, the master has already received one byte from the slave. The master
read interrupt flag is set, and the master must prepare to receive new data. The master must
respond to each byte with ACK or NACK. Indicating a NACK might not be successfully exe-
cuted, as arbitration can be lost during the transmission. If a collision is detected, the master
loses arbitration and the arbitration lost flag is set.
The TWI slave is byte-oriented with optional interrupts after each byte. There are separate slave
data and address/stop interrupts. Interrupt flags can also be used for polled operation. There are
dedicated status flags for indicating ACK/NACK received, clock hold, collision, bus error, and
read/write direction.
When an interrupt flag is set, the SCL line is forced low. This will give the slave time to respond
or handle data, and will in most cases require software interaction.
slave operation. The diamond shapes symbols (SW) indicate where software interaction is
required.
Atmel AVR XMEGA B
Figure
19-13. shows the TWI
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