ATxmega64B3 Atmel Corporation, ATxmega64B3 Datasheet - Page 51

• Manufacturer Part Number: ATxmega64B3
• Manufacturer: Atmel Corporation

Specifications of ATxmega64B3

• Flash (kbytes): 64 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 36
• Ext Interrupts: 36
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 2
• Twi (i2c): 1
• Uart: 1
• Segment Lcd: 100
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 2
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

5.4
5.5
5.6
8291A–AVR–10/11
Transfer Triggers
Addressing
Priority Between Channels
Figure 5-2.
DMA transfers can be started only when a DMA transfer request is detected. A transfer request
can be triggered from software, from an external trigger source (peripheral), or from an event.
There are dedicated source trigger selections for each DMA channel. The available trigger
sources may vary from device to device, depending on the modules or peripherals that exist in
the device. Using a transfer trigger for a module or peripherals that does not exist will have no
effect. For a list of all transfer triggers, refer to
60.
By default, a trigger starts a block transfer operation. When the block transfer is complete, the
channel is automatically disabled. When enabled again, the channel will wait for the next block
transfer trigger. It is possible to select the trigger to start a burst transfer instead of a block trans-
fer. This is called a single-shot transfer, and for each trigger only one burst is transferred. When
repeat mode is enabled, the next block transfer does not require a transfer trigger. It will start as
soon as the previous block is done.
If the trigger source generates a transfer request during an ongoing transfer, this will be kept
pending, and the transfer can start when the ongoing one is done. Only one pending transfer
can be kept, and so if the trigger source generates more transfer requests when one is already
pending, these will be lost.
The source and destination address for a DMA transfer can either be static or automatically
incremented or decremented, with individual selections for source and destination. When
address increment or decrement is used, the default behaviour is to update the address after
each access. The original source and destination addresses are stored by the DMA controller,
and so the source and destination addresses can be individually configured to be reloaded at
the following points:
If several channels request a data transfer at the same time, a priority scheme is available to
determine which channel is allowed to transfer data. Application software can decide whether
• End of each burst transfer
• End of each block transfer
• End of transaction
• Never reloaded
Four-byte burst mode
DMA transaction.
Burst transfer
Block size: 12 bytes
DMA transaction
”TRIGSRC – Trigger Source Register” on page
Repeat count: 2
Atmel AVR XMEGA B
Block transfer
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