ATtiny2313A Atmel Corporation, ATtiny2313A Datasheet - Page 24

• Manufacturer Part Number: ATtiny2313A
• Manufacturer: Atmel Corporation

Specifications of ATtiny2313A

• Flash (kbytes): 2 Kbytes
• Pin Count: 20
• Max. Operating Frequency: 20 MHz
• Cpu: 8-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 18
• Ext Interrupts: 18
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Twi (i2c): 1
• Uart: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 0.12
• Eeprom (bytes): 128
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 4
• Input Capture Channels: 1
• Pwm Channels: 4
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

5.4.3
24
ATtiny2313A/4313
EECR – EEPROM Control Register
• Bits 7, 6 – Res: Reserved Bit
These bits are reserved and will always read zero.
• Bits 5, 4 – EEPM1 and EEPM0: EEPROM Programming Mode Bits
The EEPROM Programming mode bits setting defines which programming action that will be
triggered when writing EEPE. It is possible to program data in one atomic operation (erase the
old value and program the new value) or to split the Erase and Write operations in two different
operations. The Programming times for the different modes are shown in
Table 5-4.
When EEPE is set any write to EEPMn will be ignored.
During reset, the EEPMn bits will be reset to 0b00 unless the EEPROM is busy programming.
• Bit 3 – EERIE: EEPROM Ready Interrupt Enable
Writing this bit to one enables the EEPROM Ready Interrupt. Provided the I-bit in SREG is set,
the EEPROM Ready Interrupt is triggered when non-volatile memory is ready for programming.
Writing this bit to zero disables the EEPROM Ready Interrupt.
• Bit 2 – EEMPE: EEPROM Master Program Enable
The EEMPE bit determines whether writing EEPE to one will have effect or not.
When EEMPE is set and EEPE written within four clock cycles the EEPROM at the selected
address will be programmed. Hardware clears the EEMPE bit to zero after four clock cycles.
If EEMPE is zero the EEPE bit will have no effect.
• Bit 1 – EEPE: EEPROM Program Enable
This is the programming enable signal of the EEPROM. The EEMPE bit must be set before
EEPE is written, or EEPROM will not be programmed.
When EEPE is written, the EEPROM will be programmed according to the EEPMn bit settings.
When EEPE has been set, the CPU is halted for two cycles before the next instruction is exe-
cuted. After the write access time has elapsed, the EEPE bit is cleared by hardware.
Note that an EEPROM write operation blocks all software programming of Flash, fuse bits, and
lock bits.
Bit
0x1C (0x3C)
Read/Write
Initial Value
EEPM1
0
0
1
1
EEPM0
EEPROM Programming Mode Bits and Programming Times
0
1
0
1
R
7
–
0
Programming Time
R
6
–
0
3.4 ms
1.8 ms
1.8 ms
–
EEPM1
R/W
5
X
EEPM0
R/W
X
4
Operation
Erase and Write in one operation (Atomic Operation)
Erase Only
Write Only
Reserved for future use
EERIE
R/W
3
0
EEMPE
R/W
2
0
EEPE
R/W
X
1
Table
EERE
R/W
5-4.
0
0
8246B–AVR–09/11
EECR