ATtiny2313A Atmel Corporation, ATtiny2313A Datasheet - Page 147

• Manufacturer Part Number: ATtiny2313A
• Manufacturer: Atmel Corporation

Specifications of ATtiny2313A

• Flash (kbytes): 2 Kbytes
• Pin Count: 20
• Max. Operating Frequency: 20 MHz
• Cpu: 8-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 18
• Ext Interrupts: 18
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Twi (i2c): 1
• Uart: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 0.12
• Eeprom (bytes): 128
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 4
• Input Capture Channels: 1
• Pwm Channels: 4
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

15.4
15.5
8246B–AVR–09/11
SPI Data Modes and Timing
Frame Formats
There are four combinations of XCK (SCK) phase and polarity with respect to serial data, which
are determined by control bits UCPHA and UCPOL. The data transfer timing diagrams are
shown in
nal, ensuring sufficient time for data signals to stabilize. The UCPOL and UCPHA functionality is
summarized in
ongoing communication for both the Receiver and Transmitter.
Table 15-2.
Figure 15-1. UCPHA and UCPOL data transfer timing diagrams.
A serial frame for the MSPIM is defined to be one character of 8 data bits. The USART in MSPIM
mode has two valid frame formats:
A frame starts with the least or most significant data bit. Then the next data bits, up to a total of
eight, are succeeding, ending with the most or least significant bit accordingly. When a complete
frame is transmitted, a new frame can directly follow it, or the communication line can be set to
an idle (high) state.
The UDORD bit in UCSRC sets the frame format used by the USART in MSPIM mode. The
Receiver and Transmitter use the same setting. Note that changing the setting of any of these
bits will corrupt all ongoing communication for both the Receiver and Transmitter.
• 8-bit data with MSB first
• 8-bit data with LSB first
UCPOL
BAUD
f
UBRR
OSC
0
0
1
1
Figure
XCK
Data setup (TXD)
Data sample (RXD)
Data setup (TXD)
Data sample (RXD)
XCK
UCPOL and UCPHA Functionality-
Table
15-1. Data bits are shifted out and latched in on opposite edges of the XCK sig-
UCPHA
Baud rate (in bits per second, bps)
System Oscillator clock frequency
Contents of the UBRRH and UBRRL Registers, (0-4095)
15-2. Note that changing the setting of any of these bits will corrupt all
0
1
0
1
UCPOL=0
SPI Mode
0
1
2
3
Leading Edge
Sample (Rising)
Setup (Rising)
Sample (Falling)
Setup (Falling)
Data setup (TXD)
Data sample (RXD)
Data setup (TXD)
Data sample (RXD)
XCK
XCK
ATtiny2313A/4313
Trailing Edge
Setup (Falling)
Sample (Falling)
Setup (Rising)
Sample (Rising)
UCPOL=1
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