ATtiny2313A Atmel Corporation, ATtiny2313A Datasheet - Page 156
ATtiny2313A
Manufacturer Part Number
ATtiny2313A
Description
Manufacturer
Atmel Corporation
Specifications of ATtiny2313A
Flash (kbytes)
2 Kbytes
Pin Count
20
Max. Operating Frequency
20 MHz
Cpu
8-bit AVR
Hardware Qtouch Acquisition
No
Max I/o Pins
18
Ext Interrupts
18
Usb Speed
No
Usb Interface
No
Spi
2
Twi (i2c)
1
Uart
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
0.12
Eeprom (bytes)
128
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
2
Output Compare Channels
4
Input Capture Channels
1
Pwm Channels
4
32khz Rtc
No
Calibrated Rc Oscillator
Yes
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16. USI – Universal Serial Interface
16.1
16.2
156
Features
Overview
ATtiny2313A/4313
•
•
•
•
•
•
The Universal Serial Interface (USI), provides the basic hardware resources needed for serial
communication. Combined with a minimum of control software, the USI allows significantly
higher transfer rates and uses less code space than solutions based on software only. Interrupts
are included to minimize the processor load.
A simplified block diagram of the USI is shown in
refer to
listed in the
Figure 16-1. Universal Serial Interface, Block Diagram
The 8-bit USI Data Register (USIDR) contains the incoming and outgoing data. It is directly
accessible via the data bus but a copy of the contents is also placed in the USI Buffer Register
(USIBR) where it can be retrieved later. If reading the USI Data Register directly, the register
must be read as quickly as possible to ensure that no data is lost.
The most significant bit of the USI Data Register is connected to one of two output pins (depend-
ing on the mode configuration, see
latch between the output of the USI Data Register and the output pin, which delays the change
Two-wire Synchronous Data Transfer (Master or Slave)
Three-wire Synchronous Data Transfer (Master or Slave)
Data Received Interrupt
Wakeup from Idle Mode
In Two-wire Mode: Wake-up from All Sleep Modes, Including Power-down Mode
Two-wire Start Condition Detector with Interrupt Capability
“Pinout ATtiny2313A/4313” on page
“Register Description” on page
USIDR
USIBR
USISR
USICR
2
4-bit Counter
“Analog Comparator” on page
3
2
1
0
3
2
1
0
D Q
LE
163.
2. Device-specific I/O Register and bit locations are
[1]
TIM0 COMP
Figure 16-1
0
1
Two-wire Clock
Control Unit
For actual placement of I/O pins
168). There is a transparent
CLOCK
HOLD
DO
DI/SDA
USCK/SCL
8246B–AVR–09/11
(Output only)
(Input/Open Drain)
(Input/Open Drain)