ATmega6490P Atmel Corporation, ATmega6490P Datasheet - Page 98

• Manufacturer Part Number: ATmega6490P
• Manufacturer: Atmel Corporation

Specifications of ATmega6490P

• Flash (kbytes): 64 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 20 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 69
• Ext Interrupts: 32
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Twi (i2c): 1
• Uart: 1
• Segment Lcd: 160
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 4
• Input Capture Channels: 1
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

15.2.2
15.3
15.4
8284D–AVR–6/11
Timer/Counter Clock Sources
Counter Unit
Definitions
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P
The double buffered Output Compare Register (OCR0A) is compared with the Timer/Counter
value at all times. The result of the compare can be used by the Waveform Generator to gener-
ate a PWM or variable frequency output on the Output Compare pin (OC0A).
Compare Unit” on page 100.
Flag (OCF0A) which can be used to generate an Output Compare interrupt request.
Many register and bit references in this section are written in general form. A lower case “n”
replaces the Timer/Counter number, in this case 0. A lower case “x” replaces the Output Com-
pare unit number, in this case unit A. However, when using the register or bit defines in a
program, the precise form must be used, i.e., TCNT0 for accessing Timer/Counter0 counter
value and so on.
The definitions in
Table 15-1.
The Timer/Counter can be clocked by an internal or an external clock source. The clock source
is selected by the Clock Select logic which is controlled by the Clock Select (CS02:0) bits
located in the Timer/Counter Control Register (TCCR0A). For details on clock sources and pres-
caler, see
The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit.
15-2
Figure 15-2. Counter Unit Block Diagram
Signal description (internal signals):
BOTTOM
MAX
TOP
shows a block diagram of the counter and its surroundings.
count
direction
clear
”Timer/Counter Timing Diagrams” on page 107
Definitions of Timer/Counter values.
DATA BUS
The counter reaches the BOTTOM when it becomes 0x00.
The counter reaches its MAXimum when it becomes 0xFF (decimal 255).
The counter reaches the TOP when it becomes equal to the highest value in the
count sequence. The TOP value can be assigned to be the fixed value 0xFF
(MAX) or the value stored in the OCR0A Register. The assignment is depen-
dent on the mode of operation.
TCNTn
Table 15-1
are also used extensively throughout the document.
for details. The compare match event will also set the Compare
Increment or decrement TCNT0 by 1.
Select between increment and decrement.
Clear TCNT0 (set all bits to zero).
direction
count
clear
bottom
Control Logic
top
TOVn
(Int.Req.)
clk
Tn
and onwards.
Clock Select
( From Prescaler )
Detector
Edge
See ”Output
Tn
Figure
98