ATmega6490P Atmel Corporation, ATmega6490P Datasheet - Page 307

• Manufacturer Part Number: ATmega6490P
• Manufacturer: Atmel Corporation

Specifications of ATmega6490P

• Flash (kbytes): 64 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 20 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 69
• Ext Interrupts: 32
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Twi (i2c): 1
• Uart: 1
• Segment Lcd: 160
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 4
• Input Capture Channels: 1
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

Note:
Table 27-10. Read-While-Write Limit (ATmega329A/329PA/3290A/3290PA/649A/649P/6490A/6490P)
Note:
Table 27-11. Explanation of different variables used in
Note:
27.9
27.9.1
8284D–AVR–6/11
Section
Read-While-Write section (RWW)
No Read-While-Write section (NRWW)
Variable
PCMSB
PAGEMSB
ZPCMSB
ZPAGEMSB
PCPAGE
PCWORD
1. The different BOOTSZ Fuse configurations are shown in
1. For details about these two section, see
1. Z0: should be zero for all SPM commands, byte select for the LPM instruction. See
Register Description
SPMCSR – Store Program Memory Control and Status Register
Write Section” on page
gramming” on page 299
(ATmega329A/329PA/3290A/3290PA/649A/649P/6490A/6490P)
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P
PC[13:6]
PC[5:0]
13
The Store Program Memory Control and Status Register contains the control bits needed to con-
trol the Boot Loader operations.
• Bit 7 – SPMIE: SPM Interrupt Enable
When the SPMIE bit is written to one, and the I-bit in the Status Register is set (one), the SPM
ready interrupt will be enabled. The SPM ready Interrupt will be executed as long as the SPMEN
bit in the SPMCSR Register is cleared.
5
Bit
0x37 (0x57)
Read/Write
Initial Value
295.
for details about the use of Z-pointer during Self-Programming.
Corresponding
Z-value
SPMIE
Z14:Z7
Z6:Z1
R/W
Z14
7
0
Z6
”NRWW – No Read-While-Write Section” on page 295
RWWSB
R
6
0
Most significant bit in the Program Counter. (Program Counter is 14 bits
PC[13:0])
Most significant bit which is used to address the words within one page
(64 words in a page requires six/seven bits PC [5:0]).
Bit in Z-register that is mapped to PCMSB. Because Z0 is not used, the
ZPCMSB equals PCMSB + 1.
Bit in Z-register that is mapped to PCMSB. Because Z0 is not used, the
ZPAGEMSB equals PAGEMSB + 1.
Program Counter page address: Page select, for Page Erase and Page
Write
Program Counter word address: Word select, for filling temporary buffer
(must be zero during Page Write operation)
Figure 27-3 on page 300
Pages
5
–
R
0
224
Figure 27-2
32
RWWSRE
R/W
4
0
Address
0x0000 - 0x37FF
0x3800 - 0x3FFF
BLBSET
(1)
R/W
3
0
and the mapping to the Z-pointer
Description
”Addressing the Flash During Self-Pro-
PGWRT
R/W
2
0
PGERS
and
R/W
1
0
”RWW – Read-While-
(1)
SPMEN
R/W
0
0
SPMCSR
307