ATmega6490P Atmel Corporation, ATmega6490P Datasheet - Page 147

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ATmega6490P

Manufacturer Part Number
ATmega6490P
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of ATmega6490P

Flash (kbytes)
64 Kbytes
Pin Count
100
Max. Operating Frequency
20 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
69
Ext Interrupts
32
Usb Speed
No
Usb Interface
No
Spi
2
Twi (i2c)
1
Uart
1
Segment Lcd
160
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
4
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
4
Input Capture Channels
1
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes

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18. 8-bit Timer/Counter2 with PWM and Asynchronous Operation
18.1
18.2
18.2.1
8284D–AVR–6/11
Features
Overview
Registers
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P
Timer/Counter2 is a general purpose, single compare unit, 8-bit Timer/Counter module. A simpli-
fied block diagram of the 8-bit Timer/Counter is shown in
of I/O pins, refer to
bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed
in the
Figure 18-1. 8-bit Timer/Counter Block Diagram
The Timer/Counter (TCNT2) and Output Compare Register (OCR2A) are 8-bit registers. Inter-
rupt request (shorten as Int.Req.) signals are all visible in the Timer Interrupt Flag Register
Single Compare Unit Counter
Clear Timer on Compare Match (Auto Reload)
Glitch-free, Phase Correct Pulse Width Modulator (PWM)
Frequency Generator
10-bit Clock Prescaler
Overflow and Compare Match Interrupt Sources (TOV2 and OCF2A)
Allows Clocking from External 32kHz Watch Crystal Independent of the I/O Clock
”Register Description” on page
Status flags
”Pin Configurations” on page
Timer/Counter
TCNTn
OCRnx
=
ASSRn
direction
count
clear
BOTTOM
Synchronized Status flags
= 0
161.
Control Logic
=
TCCRnx
TOP
asynchronous mode
0xFF
select (ASn)
2. CPU accessible I/O Registers, including I/O
clk
Tn
Synchronization Unit
OCnx
(Int.Req.)
Figure
Generation
Prescaler
Waveform
18-1. For the actual placement
Oscillator
T/C
OCnx
clk
TOVn
(Int.Req.)
clk
clk
ASY
I/O
I/O
TOSC1
TOSC2
147

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