ATmega6490P Atmel Corporation, ATmega6490P Datasheet - Page 22

• Manufacturer Part Number: ATmega6490P
• Manufacturer: Atmel Corporation

Specifications of ATmega6490P

• Flash (kbytes): 64 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 20 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 69
• Ext Interrupts: 32
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Twi (i2c): 1
• Uart: 1
• Segment Lcd: 160
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 4
• Input Capture Channels: 1
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

8.3
8.3.1
8284D–AVR–6/11
EEPROM Data Memory
EEPROM Read/Write Access
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P
Figure 8-3.
The ATmega169A/169PA/329A/329PA/3290A/3290PA/649A/649P/6490A/6490P contains
512/1K/2K bytes of data EEPROM memory. It is organized as a separate data space, in which
single bytes can be read and written. The EEPROM has an endurance of at least 100,000
write/erase cycles. The access between the EEPROM and the CPU is described in the follow-
ing, specifying the EEPROM Address Registers, the EEPROM Data Register, and the EEPROM
Control Register.
For a detailed description of SPI, JTAG and Parallel data downloading to the EEPROM, see
Table 28-9 on page
gramming Parameters, Pin Mapping, and Commands” on page 314
The EEPROM Access Registers are accessible in the I/O space.
The write access time for the EEPROM is given in
however, lets the user software detect when the next byte can be written. If the user code con-
tains instructions that write the EEPROM, some precautions must be taken. In heavily filtered
power supplies, V
some period of time to run at a voltage lower than specified as minimum for the clock frequency
used. See
these situations.
In order to prevent unintentional EEPROM writes, a specific write procedure must be followed.
When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is
executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next
instruction is executed.
The following procedure should be followed when writing the EEPROM (the order of steps 3 and
4 is not essential). See
register bit.
”Preventing EEPROM Corruption” on page 25
Address
clk
On-chip Data SRAM Access Cycles
Data
Data
WR
CPU
RD
CC
315,
is likely to rise or fall slowly on power-up/down. This causes the device for
”Register Description” on page 27
”Programming via the JTAG Interface” on page
Compute Address
T1
Memory Access Instruction
Address valid
Table 8-1 on page
T2
for details on how to avoid problems in
for supplementary description for each
Next Instruction
respectively.
T3
23. A self-timing function,
331, and
”Parallel Pro-
22