ATmega32U2 Atmel Corporation, ATmega32U2 Datasheet - Page 58
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ATmega32U2
Manufacturer Part Number
ATmega32U2
Description
Manufacturer
Atmel Corporation
Specifications of ATmega32U2
Flash (kbytes)
32 Kbytes
Pin Count
32
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
12
Hardware Qtouch Acquisition
No
Max I/o Pins
22
Ext Interrupts
20
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
2
Uart
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
1
Eeprom (bytes)
1024
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
2
Output Compare Channels
5
Input Capture Channels
1
Pwm Channels
4
32khz Rtc
No
Calibrated Rc Oscillator
Yes
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Table 10-3.
7799D–AVR–11/10
WDP3
0
0
0
0
0
0
0
0
1
1
WDP2
Watchdog Timer Prescale Select, DIV = 0 (CLKwdt = CLK128 / 1)
0
0
0
0
1
1
1
1
0
0
WDP1
0
0
1
1
0
0
1
1
0
0
• Bit 3 - WDEWIF: Watchdog Early Warning Interrupt Flag
This bit is set when a first time-out occurs in the Watchdog Timer and if the WDEWIE bit is
enabled. WDEWIF is automatically cleared by hardware when executing the corresponding
interrupt handling vector. Alternatively, WDIF can be cleared by writing a logic one to the flag.
When the I-bit in SREG and WDEWIE are set, the Watchdog Time-out Interrupt is executed.
• Bit 2 - WDEWIE: Watchdog Early Warning Interrupt Enable
When this bit has been set by software, an interrupt will be generated on the watchdog interrupt
vector when the Early warning flag is set to one by hardware.
• Bit 1:0 - WCLKD[1:0]: Watchdog Timer Clock Divider
Table 10-2.
WCLKD2
WDP0
0
0
0
0
1
1
1
1
0
1
0
1
0
1
0
1
0
1
Watchdog Timer Clock Divider Configuration
Number of WDT Oscillator
Cycles before 1st time-out
1024K (1048576) cycles
128K (131072) cycles
256K (262144) cycles
512K (524288) cycles
16K (16384) cycles
32K (32768) cycles
64K (65536) cycles
2K (2048) cycles
4K (4096) cycles
8K (8192) cycles
(Early warning)
WCLKD1
0
0
1
1
0
0
1
1
WCLKD0
0
1
0
1
0
1
0
1
Early warning Typical
ATmega8U2/16U2/32U2
Time-out at
V
CC
0.125 s
16 ms
32 ms
64 ms
0.25 s
0.5 s
1.0 s
2.0 s
4.0 s
8.0 s
Mode
Clk
Clk
Clk
Clk
Clk
Clk
Clk
Clk
= 5.0V
WDT
WDT
WDT
WDT
WDT
WDT
WDT
WDT
= Clk
= Clk
= Clk
= Clk
= Clk
= Clk
= Clk
= Clk
128k
128k
128k
128k
128k
128k
128k
128k
Reset/Interrupt Typical
/ 3
/ 5
/ 7
/ 9
/ 11
/ 13
/ 15
Time-out at
V
Watchdog
CC
128 ms
0.250 s
32 ms
64 ms
16.0 s
0.5 s
1.0 s
2.0 s
4.0 s
8.0 s
= 5.0V
58
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