ATmega32U2 Atmel Corporation, ATmega32U2 Datasheet - Page 133

• Manufacturer Part Number: ATmega32U2
• Manufacturer: Atmel Corporation

Specifications of ATmega32U2

• Flash (kbytes): 32 Kbytes
• Pin Count: 32
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 12
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 22
• Ext Interrupts: 20
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 2
• Uart: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 1
• Eeprom (bytes): 1024
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 5
• Input Capture Channels: 1
• Pwm Channels: 4
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

16.11.2
7799D–AVR–11/10
TCCR1B – Timer/Counter1 Control Register B
• Bit 7 – ICNCn: Input Capture Noise Canceler
Setting this bit (to one) activates the Input Capture Noise Canceler. When the Noise Canceler is
activated, the input from the Input Capture Pin (ICPn) is filtered. The filter function requires four
successive equal valued samples of the ICPn pin for changing its output. The input capture is
therefore delayed by four Oscillator cycles when the noise canceler is enabled.
• Bit 6 – ICESn: Input Capture Edge Select
This bit selects which edge on the Input Capture Pin (ICPn) that is used to trigger a capture
event. When the ICESn bit is written to zero, a falling (negative) edge is used as trigger, and
when the ICESn bit is written to one, a rising (positive) edge will trigger the capture.
When a capture is triggered according to the ICESn setting, the counter value is copied into the
Input Capture Register (ICRn). The event will also set the Input Capture Flag (ICFn), and this
can be used to cause an Input Capture Interrupt, if this interrupt is enabled.
When the ICRn is used as TOP value (see description of the WGMn[3:0] bits located in the
TCCRnA and the TCCRnB Register), the ICPn is disconnected and consequently the input cap-
ture function is disabled.
• Bit 5 – Reserved Bit
This bit is reserved for future use. For ensuring compatibility with future devices, this bit must be
written to zero when TCCRnB is written.
• Bit 4:3 – WGMn[3:2]: Waveform Generation Mode
See TCCRnA Register description.
• Bit 2:0 – CSn[2:0]: Clock Select
The three clock select bits select the clock source to be used by the Timer/Counter, see
15-1
Table 16-5.
Bit
(0x81)
Read/Write
Initial Value
CSn2
0
0
0
0
1
1
1
1
and
Figure
CSn1
0
0
1
1
0
0
1
1
Clock Select Bit Description
ICNC1
R/W
15-2.
7
0
CSn0
0
1
0
1
0
1
0
1
ICES1
R/W
6
0
Description
No clock source. (Timer/Counter stopped)
clk
clk
clk
clk
clk
External clock source on Tn pin. Clock on falling edge
External clock source on Tn pin. Clock on rising edge
I/O
I/O
I/O
I/O
I/O
R
5
–
0
/1 (No prescaling
/8 (From prescaler)
/64 (From prescaler)
/256 (From prescaler)
/1024 (From prescaler)
WGM13
R/W
4
0
ATmega8U2/16U2/32U2
WGM12
R/W
3
0
CS12
R/W
2
0
CS11
R/W
1
0
CS10
R/W
0
0
TCCR1B
Figure
133