ATmega32U2 Atmel Corporation, ATmega32U2 Datasheet - Page 215
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ATmega32U2
Manufacturer Part Number
ATmega32U2
Description
Manufacturer
Atmel Corporation
Specifications of ATmega32U2
Flash (kbytes)
32 Kbytes
Pin Count
32
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
12
Hardware Qtouch Acquisition
No
Max I/o Pins
22
Ext Interrupts
20
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
2
Uart
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
1
Eeprom (bytes)
1024
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
2
Output Compare Channels
5
Input Capture Channels
1
Pwm Channels
4
32khz Rtc
No
Calibrated Rc Oscillator
Yes
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21.18.11 UECFG0X – USB Endpoint Configuration 0 Register
7799D–AVR–11/10
• Bit 4 – STALLRQC: STALL Request Clear Handshake Bit
Writing this bit to one disables the pending STALL handshake mechanism triggered by
STALLRQ bit. This bit can not be write to zero, it is cleared by hardware immediately after the
write to one operation.
See
• Bit 3 – RSTDT: Reset Data Toggle Bit
Writing this bit to one allows to reset the data toggle bit field for the selected endpoint. This bit
can not be write to zero, it is cleared by hardware immediately after the write to one operation.
• Bits 2:1 – Res: Reserved
These bits are reserved and will always read as zero.
• Bit 0 – EPEN: Endpoint Enable Bit
Writing this bit to one enables the selected endpoint. When the endpoint is enabled it can be
configured and used by the USB controller. Endpoint 0 shall always be enabled after a hardware
or USB reset and participate in the device configuration. Writing this bit to zero disables the cur-
rent endpoint.
See
• Bit 7:6 – EPTYPE[1:0]: Endpoint Type Bits
These bits configure the endpoint type for the selected endpoint as shown in
Table 21-2.
• Bits 5:1 – Res: Reserved
These bits are reserved and will always read as zero.
• Bit 0 – EPDIR: Endpoint Direction Bit
Writing this bit to one configures the selected endpoint in the IN direction. Writing this bit to zero
configure the endpoint in the OUT direction. This bit is relevant for bulk, interrupt or isochronous
endpoints. Using this bit with a control endpoint has no effect (control endpoints are
bidirectional).
Bit
(0xEC)
Read/Write
Initial Value
“STALL request” on page 201
“Endpoint activation” on page 198
EPTYPE1
0
0
1
1
R/W
7
0
EPTYPE1:0
EPTYPE[1:0] Bits Settings
R/W
6
0
R
5
0
-
EPTYPE0
for more details.
0
1
0
1
for more details.
R
4
0
-
Control Type
Isochronous Type
Bulk Type
Interrupt Type
Endpoint Type Configuration
ATmega8U2/16U2/32U2
R
3
0
-
R
2
0
-
R
1
0
-
Table
EPDIR
R/W
0
0
21-2.
UECFG0X
215
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