ATmega32U2 Atmel Corporation, ATmega32U2 Datasheet - Page 20
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ATmega32U2
Manufacturer Part Number
ATmega32U2
Description
Manufacturer
Atmel Corporation
Specifications of ATmega32U2
Flash (kbytes)
32 Kbytes
Pin Count
32
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
12
Hardware Qtouch Acquisition
No
Max I/o Pins
22
Ext Interrupts
20
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
2
Uart
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
1
Eeprom (bytes)
1024
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
2
Output Compare Channels
5
Input Capture Channels
1
Pwm Channels
4
32khz Rtc
No
Calibrated Rc Oscillator
Yes
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7.4.1
7.5
7.5.1
7.5.2
7799D–AVR–11/10
Register Description
General Purpose I/O Registers
EEARH and EEARL – The EEPROM Address Register
EEDR – The EEPROM Data Register
Extended I/O space from 0x60 - 0x1FF in SRAM, only the ST/STS/STD and LD/LDS/LDD
instructions can be used.
For compatibility with future devices, reserved bits should be written to zero if accessed.
Reserved I/O memory addresses should never be written.
Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most
other AVRs, the CBI and SBI instructions will only operate on the specified bit, and can therefore
be used on registers containing such Status Flags. The CBI and SBI instructions work with reg-
isters 0x00 to 0x1F only.
The I/O and peripherals control registers are explained in later sections.
The ATmega8U2/16U2/32U2 contains three General Purpose I/O Registers. These registers
can be used for storing any information, and they are particularly useful for storing global vari-
ables and Status Flags. General Purpose I/O Registers within the address range 0x00 - 0x1F
are directly bit-accessible using the SBI, CBI, SBIS, and SBIC instructions.
• Bits 15:12 – Res: Reserved Bits
These bits are reserved and will always read as zero.
• Bits 11:0 – EEAR[8:0]: EEPROM Address
The EEPROM Address Registers – EEARH and EEARL specify the EEPROM address in the
512 bytes EEPROM space. The EEPROM data bytes are addressed linearly between 0 and
512. The initial value of EEAR is undefined. A proper value must be written before the EEPROM
may be accessed.
• Bits 7:0 – EEDR[7:0]: EEPROM Data
For the EEPROM write operation, the EEDR Register contains the data to be written to the
EEPROM in the address given by the EEAR Register. For the EEPROM read operation, the
EEDR contains the data read out from the EEPROM at the address given by EEAR.
Bit
0x22 (0x42)
0x21 (0x41)
Read/Write
Initial Value
Bit
0x20 (0x40)
Read/Write
Initial Value
15
EEAR7
MSB
R/W
R/W
R
X
–
7
0
7
0
14
EEAR6
R/W
R/W
R
–
6
0
X
6
0
13
EEAR5
R/W
R/W
R
–
5
0
X
5
0
12
EEAR4
R/W
R/W
R
X
–
4
0
4
0
11
EEAR11
ATmega8U2/16U2/32U2
EEAR3
R/W
R/W
R/W
X
X
3
3
0
10
EEAR10
EEAR2
R/W
R/W
R/W
2
X
X
2
0
9
EEAR9
EEAR1
R/W
R/W
R/W
1
0
1
X
X
8
EEAR8
EEAR0
LSB
R/W
R/W
R/W
X
X
0
0
0
EEDR
EEARH
EEARL
20
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