ATmega32U2 Atmel Corporation, ATmega32U2 Datasheet - Page 57

• Manufacturer Part Number: ATmega32U2
• Manufacturer: Atmel Corporation

Specifications of ATmega32U2

• Flash (kbytes): 32 Kbytes
• Pin Count: 32
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 12
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 22
• Ext Interrupts: 20
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 2
• Uart: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 1
• Eeprom (bytes): 1024
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 5
• Input Capture Channels: 1
• Pwm Channels: 4
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

10.5.3
7799D–AVR–11/10
WDTCKD – Watchdog Timer Clock Divider Register
function of the Watchdog System Reset mode. If the interrupt is not executed before the next
time-out, a System Reset will be applied.
Table 10-1.
• Bit 4 - WDCE: Watchdog Change Enable
This bit is used in timed sequences for changing WDE and prescaler bits. To clear the WDE bit,
and/or change the prescaler bits, WDCE must be set.
Once written to one, hardware will clear WDCE after four clock cycles.
• Bit 3 - WDE: Watchdog System Reset Enable
WDE is overridden by WDRF in MCUSR. This means that WDE is always set when WDRF is
set. To clear WDE, WDRF must be cleared first. This feature ensures multiple resets during con-
ditions causing failure, and a safe start-up after the failure.
• Bit 5, 2:0 - WDP[3:0]: Watchdog Timer Prescaler 3, 2, 1 and 0
The WDP3..0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is run-
ning. The different prescaling values and their corresponding time-out periods are shown in
Table on page
• Bit 7:6 - Res: Reserved bits
These bits are reserved and will always read as zero.
• Bit 5 - WDEWIFCL: Watchdog Early Warning Flag Clear Mode
When this bit has been set by software, the WDEWIF interrupt flag is not cleared by hardware
when entering the Watchdog Interrupt subroutine (it has to be cleared by software by writing a
logic one to the flag).
When cleared, the WDEWIF is cleared by hardware when executing the corresponding interrupt
handling vector.
• Bit 4 - WCLKD2 bit: Watchdog Timer Clock Divider
See
Bit
(0x62)
Read/Write
Initial Value
1 (unprogrammed)
1 (unprogrammed)
1 (unprogrammed)
1 (unprogrammed)
0 (programmed)
WDTON (Fuse)
“Bit 1:0 - WCLKD[1:0]: Watchdog Timer Clock Divider” on page
Watchdog Timer Configuration
R
7
0
-
58.
R
6
0
-
WDE
0
0
1
1
x
WIFCM
WDE-
R/W
5
0
WDIE
0
1
0
1
x
WCLKD2
R/W
4
0
Mode
Stopped
Interrupt Mode
System Reset Mode
Interrupt and System
Reset Mode
System Reset Mode
WDEWIF
R/W
ATmega8U2/16U2/32U2
3
0
WDEWIE
R/W
2
0
WCLKD1
58.
R/W
1
0
Action on 2x Time-out
None
Interrupt
Reset
Interrupt, then go to
System Reset Mode
Reset
WCLKD0
R/W
0
0
WDTCKD
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