ATmega32U2 Atmel Corporation, ATmega32U2 Datasheet - Page 204

• Manufacturer Part Number: ATmega32U2
• Manufacturer: Atmel Corporation

Specifications of ATmega32U2

• Flash (kbytes): 32 Kbytes
• Pin Count: 32
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 12
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 22
• Ext Interrupts: 20
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 2
• Uart: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 1
• Eeprom (bytes): 1024
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 5
• Input Capture Channels: 1
• Pwm Channels: 4
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

21.13.1.1
21.13.2
7799D–AVR–11/10
Example with 1 OUT data bank
RXOUTI
RXOUTI
FIFOCON
FIFOCON
Example with 2 OUT data banks
OUT
OUT
Detailed description
“Manual” mode
(to bank 0)
(to bank 0)
DATA
DATA
Each time the current bank is full, the RXOUTI and the FIFOCON bits are set. This triggers an
interrupt if the RXOUTE bit is set. The firmware can acknowledge the USB interrupt by clearing
the RXOUTI bit. The Firmware read the data and clear the FIFOCON bit in order to free the cur-
rent bank. If the OUT Endpoint is composed of multiple banks, clearing the FIFOCON bit will
switch to the next bank. The RXOUTI and FIFOCON bits are then updated by hardware in
accordance with the status of the new bank.
RXOUTI shall always be cleared before clearing FIFOCON.
The RWAL bit always reflects the state of the current bank. This bit is set if the firmware can
read data from the bank, and cleared by hardware when the bank is empty.
The data are read by the CPU, following the next flow:
• When the bank is filled by the host, an endpoint interrupt (EPINTx) is triggered, if enabled
• The CPU acknowledges the interrupt by clearing RXOUTI,
• The CPU can read the number of byte (N) in the current bank (N=BYCT),
• The CPU can read the data from the current bank (“N” read of UEDATX),
(RXOUTE set) and RXOUTI is set. The CPU can also poll RXOUTI or FIFOCON, depending
on the software architecture,
HW
HW
ACK
ACK
SW
SW
read data from CPU
OUT
BANK 0
NAK
read data from CPU
BANK 0
(to bank 1)
DATA
SW
OUT
ACK
ATmega8U2/16U2/32U2
(to bank 0)
DATA
HW
SW
HW
ACK
SW
read data from CPU
BANK 1
SW
read data from CPU
BANK 0
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