ATmega32M1 Automotive Atmel Corporation, ATmega32M1 Automotive Datasheet - Page 250
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ATmega32M1 Automotive
Manufacturer Part Number
ATmega32M1 Automotive
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT90CAN128_AUTOMOTIVE.pdf
(225 pages)
2.ATMEGA16M1_AUTOMOTIVE.pdf
(12 pages)
3.ATMEGA16M1_AUTOMOTIVE.pdf
(25 pages)
4.ATMEGA16M1_AUTOMOTIVE.pdf
(367 pages)
Specifications of ATmega32M1 Automotive
Flash (kbytes)
32 Kbytes
Pin Count
32
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
12
Hardware Qtouch Acquisition
No
Max I/o Pins
27
Ext Interrupts
27
Usb Speed
No
Usb Interface
No
Spi
1
Uart
1
Can
1
Lin
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
11
Adc Resolution (bits)
10
Adc Speed (ksps)
125
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
1
Dac Resolution (bits)
10
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
2
Eeprom (bytes)
1024
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 150
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
2
Output Compare Channels
14
Input Capture Channels
1
Pwm Channels
10
32khz Rtc
No
Calibrated Rc Oscillator
Yes
- AT90CAN128_AUTOMOTIVE PDF datasheet
- ATMEGA16M1_AUTOMOTIVE PDF datasheet #2
- ATMEGA16M1_AUTOMOTIVE PDF datasheet #3
- ATMEGA16M1_AUTOMOTIVE PDF datasheet #4
- Current page: 250 of 367
- Download datasheet (7Mb)
18.9.6
18.10 Amplifier
250
Atmel ATmega16/32/64/M1/C1
Digital Input Disable Register 1– DIDR1
• Bit 6:0 – ADC10D..8D, ACMP0D, ACMP1D, ACMP3D, AMP0PD, AMP0ND, AMP1PD,
When this bit is written logic one, the digital input buffer on the corresponding ADC pin is dis-
abled. The corresponding PIN Register bit will always read as zero when this bit is set. When
an analog signal is applied to an analog pin and the digital input from this pin is not needed,
this bit should be written logic one to reduce power consumption in the digital input buffer.
The ATmega16/32/64/M1/C1 features three differential amplified channels with programmable
5, 10, 20, and 40 gain stage.
Because the amplifiers are switching capacitor amplifiers, they need to be clocked by a syn-
chronization signal called in this document the amplifier synchronization clock. To ensure an
accurate result, the amplifier input needs to have a quite stable input value during at least 4
Amplifier synchronization clock periods. The amplifiers can run with a clock frequency of up to
250 kHz (typical value).
To ensure an accurate result, the amplifier input needs to have a quite stable input value at the
sampling point during at least 4 amplifier synchronization clock periods.
Amplified conversions can be synchronized to PSC events (See
Description in One Ramp Mode” on page 152
Centered Mode” on page
quency. In case the synchronization is done the ADC clock divided by 8, this synchronization
is done automatically by the ADC interface in such a way that the sample-and-hold occurs at a
specific phase of CK
the first free running conversion) when CK
single ended conversion (13 ADC clock cycles from the next prescaled clock cycle). A conver-
sion initiated by the user when CK
synchronization mechanism.
The normal way to use the amplifier is to select a synchronization clock via the AMPxTS1:0
bits in the AMPxCSR register. Then the amplifier can be switched on, and the amplification is
done on each synchronization event.
In order to start an amplified Analog to Digital Conversion on the amplified channel, the
ADMUX must be configured as specified on
The ADC starting requirement is done by setting the ADSC bit of the ADCSRA Register.
Until the conversion is not achieved, it is not possible to start a conversion on another channel.
In order to have a better understanding of the functioning of the amplifier synchronization, two
timing diagram examples are shown
Bit
Read/Write
Initial Value
AMP1ND, AMP2PD:
ADC10..8, ACMP0, ACMP1, ACMP3, AMP0P, AMP0N, AMP1P, AMP1N, AMP2P Digital
Input Disable
7
0
-
-
ADC2
AMP2PD
. A conversion initiated by the user (i.e., all single conversions, and
152) or to the internal clock CK
6
0
-
ACMP0D
R/W
5
0
Figure 18-15
ADC2
AMP0PD
R/W
is high will take 14 ADC clock cycles due to the
ADC2
4
0
Table 18-5 on page
is low will take the same amount of time as a
and
AMP0ND
and
R/W
3
0
“Synchronization Source Description in
Figure
ADC
ACMP1D
ADC10D
R/W
equal to eighth the ADC clock fre-
2
0
18-16.
246.
AMP1PD
ACMP3D
ADC9D
“Synchronization Source
R/W
1
0
AMP1ND
ADC8D
R/W
0
0
7647G–AVR–09/11
DIDR1
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