ATmega32M1 Automotive Atmel Corporation, ATmega32M1 Automotive Datasheet - Page 123
ATmega32M1 Automotive
Manufacturer Part Number
ATmega32M1 Automotive
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT90CAN128_AUTOMOTIVE.pdf
(225 pages)
2.ATMEGA16M1_AUTOMOTIVE.pdf
(12 pages)
3.ATMEGA16M1_AUTOMOTIVE.pdf
(25 pages)
4.ATMEGA16M1_AUTOMOTIVE.pdf
(367 pages)
Specifications of ATmega32M1 Automotive
Flash (kbytes)
32 Kbytes
Pin Count
32
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
12
Hardware Qtouch Acquisition
No
Max I/o Pins
27
Ext Interrupts
27
Usb Speed
No
Usb Interface
No
Spi
1
Uart
1
Can
1
Lin
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
11
Adc Resolution (bits)
10
Adc Speed (ksps)
125
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
1
Dac Resolution (bits)
10
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
2
Eeprom (bytes)
1024
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 150
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
2
Output Compare Channels
14
Input Capture Channels
1
Pwm Channels
10
32khz Rtc
No
Calibrated Rc Oscillator
Yes
- AT90CAN128_AUTOMOTIVE PDF datasheet
- ATMEGA16M1_AUTOMOTIVE PDF datasheet #2
- ATMEGA16M1_AUTOMOTIVE PDF datasheet #3
- ATMEGA16M1_AUTOMOTIVE PDF datasheet #4
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- Download datasheet (7Mb)
13.8.4
7647G–AVR–09/11
Phase Correct PWM Mode
This feature allows the OCRnA I/O location to be written anytime. When the OCRnA I/O loca-
tion is written the value written will be put into the OCRnA Buffer Register.
The OCRnA Compare Register will then be updated with the value in the Buffer Register at the
next timer clock cycle the TCNTn matches TOP. The update is done at the same timer clock
cycle as the TCNTn is cleared and the TOVn Flag is set.
Using the ICRn Register for defining TOP works well when using fixed TOP values. By using
ICRn, the OCRnA Register is free to be used for generating a PWM output on OCnA. How-
ever, if the base PWM frequency is actively changed (by changing the TOP value), using the
OCRnA as TOP is clearly a better choice due to its double buffer feature.
In fast PWM mode, the compare units allow generation of PWM waveforms on the OCnx pins.
Setting the COMnx1:0 bits to two will produce a non-inverted PWM and an inverted PWM out-
put can be generated by setting the COMnx1:0 to three (see
OCnx value will only be visible on the port pin if the data direction for the port pin is set as out-
put (DDR_OCnx). The PWM waveform is generated by setting (or clearing) the OCnx Register
at the compare match between OCRnx and TCNTn, and clearing (or setting) the OCnx Regis-
ter at the timer clock cycle the counter is cleared (changes from TOP to BOTTOM).
The PWM frequency for the output can be calculated by the following equation:
The N variable represents the prescaler divider (1, 8, 64, 256, or 1024).
The extreme values for the OCRnx Register represents special cases when generating a
PWM waveform output in the fast PWM mode. If the OCRnx is set equal to BOTTOM (0x0000)
the output will be a narrow spike for each TOP+1 timer clock cycle. Setting the OCRnx equal
to TOP will result in a constant high or low output (depending on the polarity of the output set
by the COMnx1:0 bits.)
A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by
setting OCnA to toggle its logical level on each compare match (COMnA1:0 = 1). This applies
only if OCR1A is used to define the TOP value (WGM13:0 = 15). The waveform generated will
have a maximum frequency of f
ture is similar to the OCnA toggle in CTC mode, except the double buffer feature of the Output
Compare unit is enabled in the fast PWM mode.
The phase correct Pulse Width Modulation or phase correct PWM mode (WGMn3:0 = 1, 2, 3,
10, or 11) provides a high resolution phase correct PWM waveform generation option. The
phase correct PWM mode is, like the phase and frequency correct PWM mode, based on a
dual-slope operation. The counter counts repeatedly from BOTTOM (0x0000) to TOP and
then from TOP to BOTTOM. In non-inverting Compare Output mode, the Output Compare
(OCnx) is cleared on the compare match between TCNTn and OCRnx while upcounting, and
set on the compare match while downcounting. In inverting Output Compare mode, the opera-
tion is inverted. The dual-slope operation has lower maximum operation frequency than single
slope operation. However, due to the symmetric feature of the dual-slope PWM modes, these
modes are preferred for motor control applications.
f
OCnxPWM
=
-------------------------------------
N
f
clk_I/O
1
+
TOP
OC
n
A
Atmel ATmega16/32/64/M1/C1
= f
clk_I/O
/2 when OCRnA is set to zero (0x0000). This fea-
Table on page
130). The actual
123
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