ATmega32M1 Automotive Atmel Corporation, ATmega32M1 Automotive Datasheet - Page 233
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ATmega32M1 Automotive
Manufacturer Part Number
ATmega32M1 Automotive
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT90CAN128_AUTOMOTIVE.pdf
(225 pages)
2.ATMEGA16M1_AUTOMOTIVE.pdf
(12 pages)
3.ATMEGA16M1_AUTOMOTIVE.pdf
(25 pages)
4.ATMEGA16M1_AUTOMOTIVE.pdf
(367 pages)
Specifications of ATmega32M1 Automotive
Flash (kbytes)
32 Kbytes
Pin Count
32
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
12
Hardware Qtouch Acquisition
No
Max I/o Pins
27
Ext Interrupts
27
Usb Speed
No
Usb Interface
No
Spi
1
Uart
1
Can
1
Lin
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
11
Adc Resolution (bits)
10
Adc Speed (ksps)
125
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
1
Dac Resolution (bits)
10
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
2
Eeprom (bytes)
1024
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 150
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
2
Output Compare Channels
14
Input Capture Channels
1
Pwm Channels
10
32khz Rtc
No
Calibrated Rc Oscillator
Yes
- AT90CAN128_AUTOMOTIVE PDF datasheet
- ATMEGA16M1_AUTOMOTIVE PDF datasheet #2
- ATMEGA16M1_AUTOMOTIVE PDF datasheet #3
- ATMEGA16M1_AUTOMOTIVE PDF datasheet #4
- Current page: 233 of 367
- Download datasheet (7Mb)
18.4
7647G–AVR–09/11
Prescaling and Conversion Timing
Figure 18-2. ADC Auto Trigger Logic
Using the ADC Interrupt Flag as a trigger source makes the ADC start a new conversion as
soon as the ongoing conversion has finished. The ADC then operates in Free Running mode,
constantly sampling and updating the ADC Data Register. The first conversion must be started
by writing a logical one to the ADSC bit in ADCSRA. In this mode the ADC will perform suc-
cessive conversions independently of whether the ADC Interrupt Flag, ADIF is cleared or not.
The free running mode is not allowed on the amplified channels.
If Auto Triggering is enabled, single conversions can be started by writing ADSC in ADCSRA
to one. ADSC can also be used to determine if a conversion is in progress. The ADSC bit will
be read as one during a conversion, independently of how the conversion was started.
Figure 18-3. ADC Prescaler
By default, the successive approximation circuitry requires an input clock frequency between
50 kHz and 2MHz to get maximum resolution. If a lower resolution than 10 bits is needed, the
input clock frequency to the ADC can be higher than 2MHz to get a higher sample rate.
The ADC module contains a prescaler, which generates an acceptable ADC clock frequency
from any CPU frequency above 100 kHz. The prescaling is set by the ADPS bits in ADCSRA.
The prescaler starts counting from the moment the ADC is switched on by setting the ADEN
bit in ADCSRA. The prescaler keeps running for as long as the ADEN bit is set, and is contin-
uously reset when ADEN is low.
ADSC
SOURCE n
ADIF
SOURCE 1
.
.
.
.
ADEN
START
ADTS[2:0]
ADPS0
ADPS1
ADPS2
CK
Atmel ATmega16/32/64/M1/C1
DETECTOR
EDGE
Reset
ADATE
7-BIT ADC PRESCALER
ADC CLOCK SOURCE
START
CONVERSION
PRESCALER
LOGIC
CLK
ADC
233
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