ATmega16M1 Atmel Corporation, ATmega16M1 Datasheet - Page 40

• Manufacturer Part Number: ATmega16M1
• Manufacturer: Atmel Corporation

Specifications of ATmega16M1

• Flash (kbytes): 16 Kbytes
• Pin Count: 32
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 12
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 27
• Ext Interrupts: 27
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Uart: 1
• Can: 1
• Lin: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 125
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 1
• Dac Resolution (bits): 10
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 1
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 14
• Input Capture Channels: 1
• Pwm Channels: 10
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

9.8.7
9.9
9.9.1
40
Register Description
ATmega16M1/32M1/64M1
On-chip Debug System
SMCR – Sleep Mode Control Register
the I/O clock (clk
be disabled. This ensures that no power is consumed by the input logic when not needed. In
some cases, the input logic is needed for detecting wake-up conditions, and it will then be
enabled. Refer to the section
input buffer is enabled and the input signal is left floating or have an analog signal level close to
V
For analog input pins, the digital input buffer should be disabled at all times. An analog signal
level close to V
input buffers can be disabled by writing to the Digital Input Disable Registers (DIDR1 and
DIDR0). Refer to “DIDR1 – Digital Input Disable Register 1” and “DIDR0 – Digital Input Disable
Register 0” on
If the On-chip debug system is enabled by OCDEN Fuse and the chip enter sleep mode, the
main clock source is enabled, and hence, always consumes power. In the deeper sleep modes,
this will contribute significantly to the total current consumption.
The Sleep Mode Control Register contains control bits for power management.
• Bits 7:4 - Res: Reserved
These bits are reserved and will always read as zero.
• Bits 3:1 – SM[2:0]: Sleep Mode Select Bits 2, 1, and 0
These bits select between the five available sleep modes as shown in
Table 9-2.
Note:
Bit
Read/Write
Initial Value
CC
/2, the input buffer will use excessive power.
SM2
0
0
0
0
1
1
1
1
1. Standby mode is only recommended for use with external crystals or resonators
Sleep Mode Select
page 262
CC
I/O
R
7
–
0
/2 on an input pin can cause significant current even in active mode. Digital
) and the ADC clock (clk
SM1
0
0
1
1
0
0
1
1
and
R
6
–
0
page 246
“I/O-Ports” on page 64
R
5
–
0
SM0
0
1
0
1
0
1
0
1
for details.
ADC
R
4
–
0
) are stopped, the input buffers of the device will
Sleep Mode
Idle
ADC Noise Reduction
Power-down
Reserved
Reserved
Reserved
Standby
Reserved
SM2
R/W
for details on which pins are enabled. If the
3
0
(1)
SM1
R/W
2
0
SM0
R/W
Table
1
0
9-2.
R/W
SE
0
0
8209D–AVR–11/10
SMCR