ATmega16M1 Atmel Corporation, ATmega16M1 Datasheet - Page 150
ATmega16M1
Manufacturer Part Number
ATmega16M1
Description
Manufacturer
Atmel Corporation
Specifications of ATmega16M1
Flash (kbytes)
16 Kbytes
Pin Count
32
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
12
Hardware Qtouch Acquisition
No
Max I/o Pins
27
Ext Interrupts
27
Usb Speed
No
Usb Interface
No
Spi
1
Uart
1
Can
1
Lin
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
11
Adc Resolution (bits)
10
Adc Speed (ksps)
125
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
1
Dac Resolution (bits)
10
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
1
Eeprom (bytes)
512
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
2
Output Compare Channels
14
Input Capture Channels
1
Pwm Channels
10
32khz Rtc
No
Calibrated Rc Oscillator
Yes
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17.16.8
17.16.9
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ATmega16M1/32M1/64M1
PCTL – PSC Control Register
PMICn – PSC Module n Input Control Register
• Bit 1:0 – Res: Reserved
These bits are reserved and will always read as zero.
• Bit 7:6 – PPRE1:0: PSC Prescaler Select
This two bits select the PSC input clock division factor. All generated waveform will be modified
by this factor.
Table 17-11. PSC Prescaler Selection
• Bit 5 – PCLKSEL: PSC Input Clock Select
This bit is used to select between CLK
Set this bit to select the fast clock input (CLK
Clear this bit to select the slow clock input (CLK
• Bit 4:2 – Res: Reserved
These bits are reserved and will always read as zero.
• Bit 1 – PCCYC: PSC Complete Cycle
When this bit is set, the PSC completes the entire waveform cycle before halt operation
requested by clearing PRUN.
• Bit 0 – PRUN: PSC Run
Writing this bit to one starts the PSC.
The Input Control Registers are used to configure the 2 PSC’s Retrigger/Fault block A & B. The
2 blocks are identical, so they are configured on the same way.
• Bit 7 – POVENn: PSC Module n Overlap Enable
Set this bit to disactivate the Overlap Protection. See
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
PPRE1
0
0
1
1
POVENn
PPRE0
0
1
0
1
PPRE1
R/W
R/W
7
0
7
0
PISELn
PPRE0
R/W
R/W
6
0
6
0
Description
No divider on PSC input clock
Divide the PSC input clock by 4
Divide the PSC input clock by 32
Divide the PSC clock by 256
PCLKSEL
PELEVn
R/W
R/W
5
0
5
0
PLL
or CLK
PFLTEn
R/W
R
4
0
4
0
-
PLL
).
IO
IO
).
clocks.
PAOCn
R/W
R
3
0
3
0
“Overlap Protection” on page
-
PRFMn2
R/W
R
2
0
2
0
-
PRFMn1
PCCYC
R/W
R/W
1
0
1
0
PRFMn0
PRUN
R/W
R/W
0
0
0
0
8209D–AVR–11/10
140.
PMICn
PCTL
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