ATmega16M1 Atmel Corporation, ATmega16M1 Datasheet
ATmega16M1
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ATmega16M1 Summary of contents
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... On-chip PLL for fast PWM ( 32MHz, 64MHz) and CPU (16MHz) • Operating Voltage: 2.7V - 5.5V • Extended Operating Temperature: – -40°C to +85°C • Core Speed Grade: – 8MHz @ 2.7 - 4.5V – 16MHz @ 4.5 - 5.5V ® ® AVR 8-bit Microcontroller (1) 8-bit Microcontroller with 16/32/64K Bytes In-System Programmable Flash ATmega16M1 ATmega32M1 ATmega64M1 Preliminary 8209D–AVR–11/10 ...
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... Pin Configurations Figure 1-1. ATmega16M1/32M1/64M1 TQFP32/QFN32 (7 × 7 mm) Package. (PCINT18/PSCIN2/OC1A/MISO_A) PD2 (PCINT19/TXD/TXLIN/OC0A/SS/MOSI_A) PD3 (PCINT9/PSCIN1/OC1B/SS_A) PC1 (PCINT10/T0/TXCAN) PC2 (PCINT11/T1/RXCAN/ICP1B) PC3 (PCINT0/MISO/PSCOUT2A) PB0 ATmega16M1/32M1/64M1 VCC 4 GND PB4 (AMP0+/PCINT4) 23 PB3 (AMP0-/PCINT3) 22 PC6 (ADC10/ACMP1/PCINT14) 21 AREF(ISRC) AGND 20 AVCC ...
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... ATmega16M1/32M1/64M1 Pinout description Mnemonic Type GND Power Ground: 0V reference AGND Power Analog Ground: 0V reference for analog part VCC Power Power Supply Analog Power Supply: This is the power supply voltage for analog part ...
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... Table 1-1. QFN32 Pin Number ATmega16M1/32M1/64M1 4 Pinout description (Continued) Mnemonic Type PSCIN1 (PSC Digital Input 1) OC1B (Timer 1 Output Compare B) PC1 I/O SS_A (Alternate SPI Slave Select) PCINT9 (Pin Change Interrupt 9) T0 (Timer 0 clock input) PC2 I/O TXCAN (CAN Transmit Output) ...
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... Note: 2. Overview The ATmega16M1/32M1/64M1 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega16M1/32M1/64M1 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. ...
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... CISC microcontrollers. The ATmega16M1/32M1/64M1 provides the following features: 16/32/64K bytes of In-System Programmable Flash with Read-While-Write capabilities, 512B/1K/2K bytes EEPROM, 1/2/4K bytes SRAM, 27 general purpose I/O lines, 32 general purpose working registers, one ...
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... As inputs, Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port C also serves the functions of special features of the ATmega16M1/32M1/64M1 as listed on page 8209D– ...
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... As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port D also serves the functions of various special features of the ATmega16M1/32M1/64M1 as listed on 2.2.6 Port E (PE2 ...
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... Note: 5. Data Retention Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85°C or 100 years at 25°C. 8209D–AVR–11/10 1. See for details ATmega16M1/32M1/64M1 9 ...
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... This allows single-cycle Arithmetic Logic Unit (ALU) operation typ- ical ALU operation, two operands are output from the Register File, the operation is executed, and the result is stored back in the Register File – in one clock cycle. ATmega16M1/32M1/64M1 10 Block Diagram of the AVR Architecture ...
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... SPI, and other I/O functions. The I/O Memory can be accessed directly the Data Space locations following those of the Register File, 0x20 - 0x5F. In addition, the ATmega16M1/32M1/64M1 has Extended I/O space from 0x60 - 0xFF in SRAM where only the ST/STS/STD and LD/LDS/LDD instructions can be used. ...
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... The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. • Bit 0 – C: Carry Flag The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. ATmega16M1/32M1/64M1 ...
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... R13 R14 R15 R16 R17 … R26 R27 R28 R29 R30 R31 Figure 6-2, each register is also assigned a data memory address, mapping them ATmega16M1/32M1/64M1 Addr. 0x00 0x01 0x02 0x0D 0x0E 0x0F 0x10 0x11 0x1A X-register Low Byte 0x1B X-register High Byte 0x1C ...
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... The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of bits actually used is implementation dependent. Note that the data space in some implementa- tions of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register will not be present. ATmega16M1/32M1/64M1 14 The X-, Y-, and Z-registers 15 ...
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... Instruction Fetch shows the internal timing concept for the Register File single clock cycle an ALU Single Cycle ALU Operation T1 clk CPU Total Execution Time Register Operands Fetch ALU Operation Execute Result Write Back ATmega16M1/32M1/64M1 SP11 SP10 SP9 SP8 SPH ...
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... When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the CLI instruction. The following example shows how this can be used to avoid interrupts during the timed EEPROM write sequence. ATmega16M1/32M1/64M1 16 for details. “Boot Loader Support – Read-While-Write Self- 270. “ ...
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... Program Counter (two bytes) is popped back from the Stack, the Stack Pointer is incremented by two, and the I-bit in SREG is set. 8209D–AVR–11/10 ; store SREG value ; disable interrupts during timed sequence ; start EEPROM write ; restore SREG value (I-bit) /* store SREG value */ /* restore SREG value (I-bit set Global Interrupt Enable ATmega16M1/32M1/64M1 17 ...
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... Boot Program section and Application Program section. The Flash memory has an endurance of at least 10,000 write/erase cycles. The ATmega16M1/32M1/64M1 Program Counter (PC bits wide, thus addressing the 16K pro- gram memory locations. The operation of Boot Program section and associated Boot Lock bits for software protection are described in detail in Programming” ...
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... X, Y, and Z are decremented or incremented. The 32 general purpose working registers, 64 I/O Registers, 160 Extended I/O Registers, and the 1/2/4K bytes of internal data SRAM in the ATmega16M1/32M1/64M1 are all accessible through all these addressing modes. The Register File is described in ter File” on page Figure 7-2 ...
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... Figure 7-3. 7.4 EEPROM Data Memory The ATmega16M1/32M1/64M1 contains 512B/1K/2K bytes of data EEPROM memory organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described in the following, specifying the EEPROM Address Regis- ters, the EEPROM Data Register, and the EEPROM Control Register ...
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... The I/O space definition of the ATmega16M1/32M1/64M1 is shown in page 320. All ATmega16M1/32M1/64M1 I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32 general purpose working registers and the I/O space. I/O registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these regis- ters, the value of single bits can be checked by using the SBIS and SBIC instructions ...
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... EEWE possible to program data in one atomic operation (erase the old value and program the new value split the Erase and Write operations in two different operations. The Programming times for the different modes are shown in ATmega16M1/32M1/64M1 22 15 ...
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... EEPROM Mode Bits Programming EEPM0 Time Operation 0 3.4ms Erase and Write in one operation (Atomic Operation) 1 1.8ms Erase Only 0 1.8ms Write Only 1 – Reserved for future use ATmega16M1/32M1/64M1 for details about Boot “Boot Loader 23 ...
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... The examples also assume that no Flash Boot Loader is present in the software. If such code is present, the EEPROM write function must also wait for any ongoing SPM command to finish. ATmega16M1/32M1/64M1 24 EEPROM Programming Time. ...
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... EECR,EEMWE ; Start eeprom write by setting EEWE sbi EECR,EEWE ret /* Wait for completion of previous write */ while(EECR & (1<<EEWE Set up address and data registers */ EEAR = uiAddress; EEDR = ucData; /* Write logical one to EEMWE */ EECR |= (1<<EEMWE); /* Start eeprom write by setting EEWE */ EECR |= (1<<EEWE); ATmega16M1/32M1/64M1 25 ...
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... Return data from data register */ return EEDR; } 7.7.4 GPIOR0 – General Purpose I/O Register 0 Bit Read/Write Initial Value 7.7.5 GPIOR1 – General Purpose I/O Register 1 Bit Read/Write Initial Value 7.7.6 GPIOR2 – General Purpose I/O Register 2 Bit Read/Write Initial Value ATmega16M1/32M1/64M1 26 r16,EEDR ; GPIOR07 GPIOR06 GPIOR05 GPIOR04 R/W R/W R/W R ...
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... Fast General I/O ADC Peripherals Modules CLK PLL clk PLL clk AVR Clock I/O Control Unit Clock Multiplexer External Clock ATmega16M1/32M1/64M1 “Power Management and CPU Core RAM ADC clk CPU clk FLASH Reset Logic Watchdog Timer Source Clock Watchdog Clock Watchdog Oscillator (Crystal ...
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... The Watchdog Oscillator is used for timing this real-time part of the start-up time. The number of WDT Oscillator cycles used for each time-out is shown in 29. The frequency of the Watchdog Oscillator is voltage dependent as shown in TBD. ATmega16M1/32M1/64M1 28 Device Clocking Options Select 1. For all fuses “1” means unprogrammed while “0” means programmed 2 ...
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... Oscillator operation, refer to the Multi-purpose Oscillator Applica- tion Note. Figure 8-2. The Oscillator can operate in three different modes, each optimized for a specific frequency range. The operating mode is selected by the fuses CKSEL3..1 as shown in 30. 8209D–AVR–11/10 ATmega16M1/32M1/64M1 Number of Watchdog Oscillator Cycles = 5.0V) Typ Time-out (V CC 4.1ms 4.3ms ...
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... Calibrated Internal RC Oscillator By default, the Internal RC OScillator provides an approximate 8.0MHz clock. Though voltage and temperature dependent, this clock can be very accurately calibrated by the user. The device is shipped with the CKDIV8 Fuse programmed. See more details. ATmega16M1/32M1/64M1 30 Crystal Oscillator Operating Modes (1) Frequency Range ...
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... PLL 8.6.1 Internal PLL The internal PLL in ATmega16M1/32M1/64M1 generates a clock frequency that is 64× multi- plied from nominally 1MHz input. The source of the 1MHz PLL input clock is the output of the internal RC Oscillator which is divided down to 1MHz. See the The PLL is locked on the RC Oscillator and adjusting the RC Oscillator via OSCCAL Register will adjust the fast peripheral clock at the same time ...
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... Internal Oscillator The 128kHz internal Oscillator is a low power Oscillator providing a clock of 128kHz. The fre- quency is nominal at 3V and 25°C. This clock is used by the Watchdog Oscillator. ATmega16M1/32M1/64M1 32 Start-up Times when the PLL is selected as system clock Start-up Time from Power-down SUT1..0 ...
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... I/O pin will be overridden when the fuse is pro- grammed. Any clock source, including internal RC Oscillator, can be selected when CLKO serves as clock output. If the System Clock Prescaler is used the divided system clock that is output (CKOUT Fuse programmed). 8209D–AVR–11/10 ATmega16M1/32M1/64M1 External Clock Drive Configuration NC External Clock ...
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... System Clock Prescaler The ATmega16M1/32M1/64M1 system clock can be divided by setting the Clock Prescale Reg- ister – CLKPR. This feature can be used to decrease power consumption when the requirement for processing power is low. This can be used with all clock source options, and it will affect the clock frequency of the CPU and all synchronous peripherals ...
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... for Fast Peripherals. After the PLL is enabled, it takes about 100ms for the PLL to lock CLKPCE – – R 36. ATmega16M1/32M1/64M1 – – PLLF PLLE PLOCK R R R – CLKPS3 ...
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... The device is shipped with the CKDIV8 Fuse programmed. Table 8-10. CLKPS3 ATmega16M1/32M1/64M1 36 Clock Prescaler Select CLKPS2 CLKPS1 ...
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... Timer Overflow and UART Transmit Complete interrupts. If wake-up from the Ana- log Comparator interrupt is not required, the Analog Comparator can be powered down by setting the ACD bit in the Analog Comparator Control and Status Register – ACSR. This will 8209D–AVR–11/10 presents the different clock systems in the ATmega16M1/32M1/64M1, Oscillators X X ...
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... PRR, puts the module in the same state as before shutdown. A full predictible behaviour of a peripheral is not guaranteed during and after a cycle of stopping and starting of its clock. So its recommended to stop a peripheral before stopping its clock with PRR register. ATmega16M1/32M1/64M1 38 , clk , and clk ...
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... ADC operation. “AC – Analog Comparator” on page 254 for details on the start-up time. “Watchdog Timer” on page 46 ATmega16M1/32M1/64M1 “ADC – Analog to Digital Converter” on for details on how to configure the Ana- “Brown-out Detection” on page 44 for details on how to configure the Watchdog Timer. ...
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... These bits select between the five available sleep modes as shown in Table 9-2. SM2 Note: ATmega16M1/32M1/64M1 40 ) and the ADC clock (clk I/O “I/O-Ports” on page input pin can cause significant current even in active mode. Digital CC page 262 and page 246 for details. 7 ...
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... Writing a logic one to this bit reduces the consumption of the ADC by stopping the clock to this module. The ADC must be disabled before using this function. The analog comparator cannot use the ADC input MUX when the clock of ADC is stopped. 8209D–AVR–11/10 ATmega16M1/32M1/64M1 ...
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... Reset Sources The ATmega16M1/32M1/64M1 has four sources of reset: • Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (V • External Reset. The MCU is reset when a low level is present on the RESET pin for longer than the minimum pulse length • ...
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... The RESET signal is activated again, without any delay, CC decreases below the detection level CCRR PORMAX V PORMIN TOUT TIME -OUT INTE R NAL ATmega16M1/32M1/64M1 DATA BUS MCU Status Register (MCUSR) Circuit Delay Counters Clock CK TIMEOUT 311. The POR is activated whenever CC 43 ...
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... MCU after the Time-out period – t Figure 10-4. External Reset During Operation 10.2.3 Brown-out Detection ATmega16M1/32M1/64M1 has an On-chip Brown-out Detection (BOD) circuit for monitoring the V level during operation by comparing fixed trigger level. The trigger level for the BOD CC can be selected by the BODLEVEL Fuses ...
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... Figure 10-6. Watchdog Reset During Operation 10.3 Internal Voltage Reference ATmega16M1/32M1/64M1 features an internal bandgap reference. This reference is used for Brown-out DetectionDetection, and it can be used as an input to the Analog Comparators or the ADC. The V internal bandgap reference. Voltage Reference Enable Signals and Start-up Time 10 ...
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... Possible Hardware fuse Watchdog always on (WDTON) for fail-safe mode 10.4.2 Overview The ATmega16M1/32M1/64M1 has an Enhanced Watchdog Timer (WDT). The WDT is a timer counting cycles of a separate on-chip 128kHz oscillator. The WDT gives an interrupt or a system reset when the counter reaches a given time-out value. In normal operation mode required that the system uses the WDR - Watchdog Timer Reset - instruction to restart the counter before the time-out value is reached ...
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... The following code example shows one assembly and one C function for turning off the Watch- dog Timer. The example assumes that interrupts are controlled (for example by disabling interrupts globally) so that no interrupts will occur during the execution of these functions. 8209D–AVR–11/10 ATmega16M1/32M1/64M1 47 ...
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... Watchdog System Reset Flag (WDRF) and the WDE control bit in the initialisation routine, even if the Watchdog is not in use. The following code example shows one assembly and one C function for changing the time-out value of the Watchdog Timer. ATmega16M1/32M1/64M1 48 (1) r16, MCUSR r16, (0xff & ...
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... Finished setting new values, used 2 cycles - ; Turn on global interrupt sei ret (1) __disable_interrupt(); __watchdog_reset(); /* Start timed equence */ WDTCSR |= (1<<WDCE) | (1<<WDE); /* Set new prescaler(time-out) value = 64K cycles (~0 WDTCSR = (1<<WDE) | (1<<WDP2) | (1<<WDP0); __enable_interrupt(); 1. The example code assumes that the part specific header file is included ATmega16M1/32M1/64M1 49 ...
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... Watchdog Timer will set WDIF. Executing the corresponding interrupt vector will clear WDIE and WDIF automatically by hardware (the Watchdog goes to System Reset Mode). This is use- ful for keeping the Watchdog Timer security while using the interrupt. To stay in Interrupt and ATmega16M1/32M1/64M1 50 7 ...
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... Interrupt Mode 1 0 System Reset Mode Interrupt and System Reset 1 1 Mode x x System Reset Mode 1. For the WDTON Fuse “1” means unprogrammed while “0” means programmed 52. ATmega16M1/32M1/64M1 Action on Time-out None Interrupt Reset Interrupt, then go to System Reset Mode Reset 51 ...
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... Table 10-2. WDP3 ATmega16M1/32M1/64M1 52 Watchdog Timer Prescale Select Number of WDT Oscillator WDP2 WDP1 WDP0 (2048) cycles (4096) cycles (8192) cycles 16K (16384) cycles 32K (32768) cycles ...
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... ATmega16M1/32M1/64M1. For a general explanation of the AVR interrupt handling, refer to “ ...
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... When the IVSEL bit in MCUCR is set, Interrupt Vectors will be moved to the start of the Boot Flash Section. The address of each Interrupt Vector will then be the address in this table added to the start address of the Boot Flash Section shows reset and Interrupt Vectors placement for the various combinations of Reset and Interrupt Vectors Placement in ATmega16M1/32M1/64M1 IVSEL Reset Address 0 ...
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... IVSEL bit in the MCUCR Register is set before any interrupts are enabled, the most typical and ATmega16M1/32M1/64M1 is: Address Labels Code ...
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... When the BOOTRST Fuse is programmed, the Boot section size set to 2 Kbytes and the IVSEL bit in the MCUCR Register is set before any interrupts are enabled, the most typical and general program setup for the Reset and Interrupt Vector Addresses in ATmega16M1/32M1/64M1 is: Address Labels Code ...
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... Application section. If Interrupt Vectors are placed in the Application section and Boot Lock bit BLB12 is programed, interrupts are disabled while executing from the Boot Loader section. Refer to the section Write Self-Programming” on page 270 ATmega16M1/32M1/64M1 ...
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... Enable change of Interrupt Vectors ldi r16, (1<<IVCE) out MCUCR, r16 ; Move interrupts to Boot Flash section ldi r16, (1<<IVSEL) out MCUCR, r16 ret C Code Example void Move_interrupts(void Enable change of Interrupt Vectors */ MCUCR = (1<<IVCE); /* Move interrupts to Boot Flash section */ MCUCR = (1<<IVSEL); } ATmega16M1/32M1/64M1 58 8209D–AVR–11/10 ...
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... Figure 12-1. Timing of a pin change interrupts PCINT[i] pin 8209D–AVR–11/10 pin_lat pin_sync PCINT[i] bit (of PCMSK clk clk PCINT[i] pin pin_lat pin_sync pcint_in[i] pcint_syn pcint_set/flag PCIF n ATmega16M1/32M1/64M1 “Clock Systems and their Distribution” on 27. 0 pcint_sync pcint_set/flag pcint_in[ clk n PCIF (interrupt flag) 59 ...
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... The Interrupt Sense Control bits in the External Interrupt Control Register A - EICRA defines whether the external interrupt is activated on rising or falling edge or level sensed. Activity on any of these pins will trigger an interrupt request even if the pin is enabled as an output. This provides a way of generating a software interrupt. ATmega16M1/32M1/64M1 ...
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... When the PCIE0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin change interrupt 0 is enabled. Any change on any enabled PCINT7:0 pin will cause an interrupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI0 Inter- rupt Vector. PCINT7:0 pins are enabled individually by the PCMSK0 Register. 8209D–AVR–11/10 ATmega16M1/32M1/64M1 – ...
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... Bit 2:0 – PCINT26:24: Pin Change Enable Mask 26:24 Each PCINT26:24-bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT26:24 is set and the PCIE3 bit in PCICR is set, pin change interrupt is enabled on the corresponding I/O pin. If PCINT23:24 is cleared, pin change interrupt on the corresponding I/O pin is disabled. ATmega16M1/32M1/64M1 – ...
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... PCINT22 PCINT21 PCINT20 R/W R/W R/W R PCINT15 PCINT14 PCINT13 PCINT12 R R/W R/W R PCINT7 PCINT6 PCINT5 PCINT4 R/W R/W R/W R ATmega16M1/32M1/64M1 PCINT19 PCINT18 PCINT17 PCINT16 R/W R/W R/W R PCINT11 PCINT10 PCINT9 PCINT8 R/W R/W R/W R PCINT3 PCINT2 PCINT1 PCINT0 R/W R/W R/W R ...
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... Refer to the individual module sections for a full description of the alternate functions. Note that enabling the alternate function of some of the port pins does not affect the use of the other pins in the port as general digital I/O. ATmega16M1/32M1/64M1 64 “Electrical Characteristics” on page 307 Pxn ...
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... I/O CLOCK I/O 1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk SLEEP, and PUD are common to all ports 83, the DDxn bits are accessed at the DDRx I/O address, the PORTxn bits ATmega16M1/32M1/64M1 Figure 13 DDxn Q CLR ...
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... This is needed to avoid metastability if the physical pin changes value near the edge of the internal clock, but it also introduces a delay. page 67 value. The maximum and minimum propagation delays are denoted t respectively. ATmega16M1/32M1/64M1 66 summarizes the control signals for the pin value. Port Pin Configurations PUD ...
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... The out instruction sets the “SYNC LATCH” signal at the positive edge of through the synchronizer is 1 system clock period. pd SYSTEM CLK r16 INSTRUCTIONS out PORTx, r16 SYNC LATCH PINxn r17 ATmega16M1/32M1/64M1 XXX in r17, PINx 0x00 t pd, max t pd, min , a single signal transition on the pin will be delayed 0xFF ...
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... Rising Edge, Falling Edge, or Any Logic Change on Pin” while the external interrupt is not enabled, the corresponding External Interrupt Flag will be set when resuming from the above mentioned sleep modes, as the clamping in these sleep modes produces the requested logic change. ATmega16M1/32M1/64M1 68 (1) r16, (1<<PB7)|(1<<PB6)|(1<<PB1)|(1<<PB0) r17, (1< ...
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... WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk SLEEP, and PUD are common to all ports. All other signals are unique for each pin summarizes the function of the overriding signals. The pin and port Figure 13-5 are not shown in the succeeding tables. The overriding signals are ATmega16M1/32M1/64M1 Figure 13-2 on page 65 PUD Q D ...
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... Refer to the alternate function description for further details. 13.3.1 Alternate Functions of Port B The Port B pins with alternate functions are shown in ATmega16M1/32M1/64M1 70 Generic Description of Overriding Signals for Alternate Functions Full Name Description If this signal is set, the pull-up enable is controlled by the PUOV Pull-up Override signal ...
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... ADC5 (Analog Input Channel5) INT1 (External Interrupt 1) ACMPN0 (Analog Comparator 0 Negative Input) PCINT2 (Pin Change Interrupt 2) MOSI (SPI Master Out Slave In) PSCOUT2B (PSC output 2B) PCINT1 (Pin Change Interrupt 1) MISO (SPI Master In Slave Out) PSCOUT2A (PSC output 2A) PCINT0 (Pin Change Interrupt 0) ATmega16M1/32M1/64M1 71 ...
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... DDB0. When the SPI is enabled as a slave, the data direction of this pin is controlled by DDB0. When the pin is forced input, the pull-up can still be controlled by the PORTB0 and PUD bits. PSCOUT2A, Output 2A of PSC. PCINT0, Pin Change Interrupt 0. ATmega16M1/32M1/64M1 72 8209D–AVR–11/10 ...
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... Overriding Signals for Alternate Functions in PB3..PB0 PB3/AMP0-/ PB2/ADC5/INT1/ PCINT3 ACMPN0/PCINT2 AMP0ND ADC5D + In1en 0 In1en INT1 AMP0- ADC5 ATmega16M1/32M1/64M1 PB5/ADC6/ PB4/AMP0+/ INT2/ACMPN1/ AMP2-/PCINT5 PCINT4 ADC6D + In2en AMP0ND In2en 0 INT2 ADC6 ...
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... AMP2+, Analog Differential Amplifier 2 Positive Input. Configure the port pin as input with the internal pull-up switched off to avoid the digital port function from interfering with the function of the Amplifier. PCINT15, Pin Change Interrupt 15. ATmega16M1/32M1/64M1 74 Port C Pins Alternate Functions Port Pin Alternate Function ...
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... OC1B, Output Compare Match B output: This pin can serve as an external output for the Timer/Counter1 Output Compare B. The pin has to be configured as an output (DDC1 set “one”) to serve this function. This pin is also the output pin for the PWM mode timer function. 8209D–AVR–11/10 ATmega16M1/32M1/64M1 75 ...
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... Table 13-7 signals shown in Table 13-7. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO ATmega16M1/32M1/64M1 76 and Table 13-8 on page 77 relate the alternate functions of Port C to the overriding Figure 13-5 on page 69. Overriding Signals for Alternate Functions in PC7..PC4 PC6/ADC10/ PC7/D2A/AMP2+/ ACMP1/ PCINT15 PCINT14 0 ...
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... Table 13-8. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO 8209D–AVR–11/10 ATmega16M1/32M1/64M1 Overriding Signals for Alternate Functions in PC3..PC0 PC3/T1/RXCAN/ PC2/T0/TXCAN/ ICP1B/PCINT11 PCINT10 PC1/PSCIN1/ PC0/INT3/ OC1B/SS_A/ PSCOUT1A/ PCINT9 PCINT8 ...
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... Ana- log Comparator. PCINT23, Pin Change Interrupt 23. • ADC3/ACMPN2/INT0/PCINT22 – Bit 6 ADC3, Analog to Digital Converter, input channel 3. ATmega16M1/32M1/64M1 78 Port D Pins Alternate Functions Alternate Function ACMP0 (Analog Comparator 0 Positive Input) ...
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... DDD3 When the SPI is enabled as a master, the data direction of this pin is controlled by DDD3. When the pin is forced input, the pull-up can still be controlled by the PORTD3 bit. PCINT19, Pin Change Interrupt 19. 8209D–AVR–11/10 ATmega16M1/32M1/64M1 79 ...
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... Table 13-10. Overriding Signals for Alternate Functions PD7..PD4 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO ATmega16M1/32M1/64M1 80 and Table 13-11 on page 81 relates the alternate functions of Port D to the overrid- Figure 13-5 on page 69. PD7/ PD6/ADC3/ ACMP0/ ACMPN2/INT0/ PCINT23 PCINT22 ...
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... OC0B (Timer 0 Output Compare B) PCINT25 (Pin Change Interrupt 25) RESET# (Reset Input) OCD (On Chip Debug I/O) PCINT24 (Pin Change Interrupt 24 the engineering samples (Parts marked AT90PWM324), the ACMPN3 alternate function is not located on PC4 located on PE2 ATmega16M1/32M1/64M1 PD1/PSCIN0/ CLKO/ PD0/PSCOUT0A/ PCINT17 XCK/PCINT16 SPE • ...
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... Table 13-13 13-5 on page Table 13-13. Overriding Signals for Alternate Functions in PE2..PE0 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO ATmega16M1/32M1/64M1 82 relates the alternate functions of Port E to the overriding signals shown in 69. PE2/ADC0/XTAL2/ PCINT26 ADC0D 0 Osc Output ...
Page 83
... PORTC – Port C Data Register Bit Read/Write Initial Value 13.4.6 DDRC – Port C Data Direction Register Bit Read/Write Initial Value 13.4.7 PINC – Port C Input Pins Address Bit Read/Write Initial Value 8209D–AVR–11/10 ATmega16M1/32M1/64M1 SPIPS – – PUD R R for more details on this feature ...
Page 84
... Bit Read/Write Initial Value 13.4.11 PORTE – Port E Data Register Bit Read/Write Initial Value 13.4.12 DDRE – Port E Data Direction Register Bit Read/Write Initial Value 13.4.13 PINE – Port E Input Pins Address Bit Read/Write Initial Value ATmega16M1/32M1/64M1 PORTD7 PORTD6 PORTD5 PORTD4 R/W R/W R/W R ...
Page 85
... I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit loca- tions are listed in the The PRTIM0 bit in Timer/Counter0 module. Figure 14-1. 8-bit Timer/Counter Block Diagram 8209D–AVR–11/10 ATmega16M1/32M1/64M1 “Pin Descriptions” on page “Register Description” on page “Power Reduction Register” on page 38 count clear ...
Page 86
... Timer/Counter Control Register (TCCR0B). For details on clock sources and pres- caler, see 14.4 Counter Unit The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. 14-2 on page 87 ATmega16M1/32M1/64M1 86 Table 14-1 are also used extensively throughout the document. Definitions The counter reaches the BOTTOM when it becomes 0x00 ...
Page 87
... Signalize that TCNT0 has reached minimum value (zero). ). clk can be generated from an external or internal clock source present or not. A CPU write overrides (has priority over) all counter clear or T0 90. shows a block diagram of the Output Compare unit. ATmega16M1/32M1/64M1 TOVn (Int.Req.) Clock Select Edge Detector clk Tn Control Logic ...
Page 88
... TCNT0 when using the Output Compare Unit, independently of whether the Timer/Counter is running or not. If the value written to TCNT0 equals the OCR0x value, the compare match will be missed, resulting in incorrect waveform generation. Similarly, do not write the TCNT0 value equal to BOTTOM when the counter is downcounting. ATmega16M1/32M1/64M1 88 DATA BUS OCRnx = ...
Page 89
... For all modes, setting the COM0x1 tells the Waveform Generator that no action on the OC0x Register performed on the next compare match. For compare output actions in the 8209D–AVR–11/10 COMnx1 Waveform COMnx0 D Generator FOCn D PORT D clk I/O See “Register Description” on page 96. ATmega16M1/32M1/64M1 Figure 14-4 shows a simplified Q 1 OCnx Pin OCnx DDR 89 ...
Page 90
... The timing diagram for the CTC mode is shown in (TCNT0) increases until a compare match occurs between TCNT0 and OCR0A, and then coun- ter (TCNT0) is cleared. ATmega16M1/32M1/64M1 90 Table 14-2 on page 96. For fast PWM mode, refer to Table 14-4 on page 89.). “ ...
Page 91
... In fast PWM mode, the counter is incremented until the counter value matches the TOP value. The counter is then cleared at the following timer clock cycle. The timing diagram for the fast 8209D–AVR–11/10 ATmega16M1/32M1/64M1 ...
Page 92
... A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by set- ting OC0x to toggle its logical level on each compare match (COM0x1:0 = 1). The waveform generated will have a maximum frequency of f ATmega16M1/32M1/64M1 92 Figure 14-6. The TCNT0 value is in the timing diagram shown as a his- ...
Page 93
... OC0x pins. Setting the COM0x1:0 bits to two will produce a non-inverted PWM. An inverted PWM output can be generated by setting the COM0x1:0 to three: Setting the COM0A0 bits to 8209D–AVR–11/10 14-7. The TCNT0 value is in the timing diagram shown as a histogram for illustrating 1 ATmega16M1/32M1/64M1 OCnx Interrupt Flag Set OCRnx Update TOVn Interrupt Flag Set (COMnx1 ...
Page 94
... MAX value in all modes other than phase correct PWM mode. Figure 14-8. Timer/Counter Timing Diagram, no Prescaling clk clk (clk I/O TCNTn TOVn ATmega16M1/32M1/64M1 94 Table 14-7 on page f OCnxPCPWM Figure 14-7 on page 93 Figure 14-8 contains timing data for basic Timer/Counter operation. The figure I/O ...
Page 95
... OCF0B in all modes and OCF0A in all modes except CTC I/O Tn /8) I/O OCRnx - 1 shows the setting of OCF0A and the clearing of TCNT0 in CTC mode and fast caler (f /8) clk_I/O I/O Tn /8) I/O TOP - 1 ATmega16M1/32M1/64M1 /8) clk_I/O MAX BOTTOM OCRnx OCRnx + 1 OCRnx Value TOP BOTTOM TOP BOTTOM + 1 /8) clk_I/O OCRnx + 2 ...
Page 96
... WGM02:0 bit setting. are set to a normal or CTC mode (non-PWM). Table 14-2. COM0A1 Table 14-3 mode. Table 14-3. COM0A1 Note: ATmega16M1/32M1/64M1 COM0A1 COM0A0 COM0B1 R/W R/W R Table 14-2 shows the COM0A1:0 bit functionality when the WGM02:0 bits Compare Output Mode, non-PWM Mode ...
Page 97
... Set OC0B on Compare Match, clear OC0B at TOP 1. A special case occurs when OCR0B equals TOP and COM0B1 is set. In this case, the Com- pare Match is ignored, but the set or clear is done at TOP. See for more details ATmega16M1/32M1/64M1 (1) “Phase Correct PWM Mode” on (1) “ ...
Page 98
... Mode Notes: ATmega16M1/32M1/64M1 98 shows the COM0B1:0 bit functionality when the WGM02:0 bits are set to phase cor- Compare Output Mode, Phase Correct PWM Mode COM0B0 Description 0 Normal port operation, OC0B disconnected 1 Reserved Clear OC0B on Compare Match when up-counting. Set OC0B on ...
Page 99
... Timer/Counter Control Register A” on page Clock Select Bit Description CS01 CS00 Description clock source (Timer/Counter stopped clk /(No prescaling) I clk /8 (From prescaler) I clk /64 (From prescaler) I/O ATmega16M1/32M1/64M1 – WGM02 CS02 CS01 R CS00 TCCR0B R/W 0 96. ...
Page 100
... OC0B pin. 14.9.6 TIMSK0 – Timer/Counter Interrupt Mask Register Bit Read/Write Initial Value • Bits 7:3 – Res: Reserved These bits are reserved and will always read as zero. ATmega16M1/32M1/64M1 100 Clock Select Bit Description (Continued) CS01 CS00 Description 0 0 clk ...
Page 101
... When the SREG I-bit, TOIE0 (Timer/Counter0 Overflow Interrupt Enable), and TOV0 are set, the Timer/Counter0 Overflow interrupt is executed. The setting of this flag is dependent of the WGM02:0 bit setting. Refer to Generation Mode Bit Description” on page 8209D–AVR–11/10 ATmega16M1/32M1/64M1 . . . 7 ...
Page 102
... I/O pins, refer to isters, including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in the The PRTIM1 bit in Timer/Counter1 module. ATmega16M1/32M1/64M1 102 “Pin Descriptions” on page “Register Description” on page “Power Reduction Register” on page 38 Figure 15-1 on page 103 ...
Page 103
... RTG Timer/Counter TCNTn = OCRnA = OCRnB ICRn TCCRnA Table 1-1 on page 3 1. Refer to for Timer/Counter1 pin placement and description The compare match event will also set the Compare Match Flag (OCFnx) ATmega16M1/32M1/64M1 (1) TOVn (Int.Req.) Clock Select clk Tn Edge Detector TOP BOTTOM ( From Prescaler ) = ...
Page 104
... The same principle can be used directly for accessing the OCRnx and ICRn Registers. Note that when using “C”, the compiler handles the 16-bit access. ATmega16M1/32M1/64M1 104 The counter reaches the BOTTOM when it becomes 0x0000 The counter reaches its MAXimum when it becomes 0xFFFF (decimal 65535) The counter reaches the TOP when it becomes equal to the highest value in the count sequence ...
Page 105
... For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR” ATmega16M1/32M1/64M1 105 ...
Page 106
... SREG = sreg; return i; } Note: The assembly code example returns the TCNTn value in the r17:r16 register pair. ATmega16M1/32M1/64M1 106 (1) (1) 1. The example code assumes that the part specific header file is included. For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” ...
Page 107
... For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR” “Timer/Counter0 and Timer/Counter1 Prescalers” on page ATmega16M1/32M1/64M1 130. 107 ...
Page 108
... There are close connections between how the counter behaves (counts) and how waveforms are generated on the Output Compare outputs OCnx. For more details about advanced counting sequences and waveform generation, see ATmega16M1/32M1/64M1 108 shows a block diagram of the counter and its surroundings. ...
Page 109
... DATA BUS TEMP (8-bit) ICRnH (8-bit) ICRnL (8-bit) ICRn (16-bit Register) WRITE Analog Comparator 1 Interrupt ICPSEL1 AC1ICE ICPnA ICPnB ATmega16M1/32M1/64M1 Figure 15-3. The elements of (8-bit) TCNTnH (8-bit) TCNTnL (8-bit) TCNTn (16-bit Counter) ICNC ICES Noise Edge ICFn (Int.Req.) Canceler ...
Page 110
... Measurement of an external signal’s duty cycle requires that the trigger edge is changed after each capture. Changing the edge sensing must be done as early as possible after the ICRn Register has been read. After a change of the edge, the Input Capture Flag (ICFn) must be ATmega16M1/32M1/64M1 110 104. ...
Page 111
... Output Compare unit. The small “n” in the register and DATA BUS TEMP (8-bit) OCRnxH Buf. (8-bit) OCRnxL Buf. (8-bit) OCRnx Buffer (16-bit Register) OCRnxH (8-bit) OCRnxL (8-bit) OCRnx (16-bit Register) TOP BOTTOM ATmega16M1/32M1/64M1 (8-bit) TCNTnH (8-bit) TCNTnL (8-bit) TCNTn (16-bit Counter) = (16-bit Comparator ) OCFnx (Int.Req.) Waveform Generator WGMn3:0 COMnx1:0 ...
Page 112
... Normal mode. The OCnx Register keeps its value even when changing between Waveform Generation modes. Be aware that the COMnx1:0 bits are not double buffered together with the compare value. Changing the COMnx1:0 bits will take effect immediately. ATmega16M1/32M1/64M1 112 104. “Accessing 16-bit Registers” ...
Page 113
... For all modes, setting the COMnx1 tells the Waveform Generator that no action on the OCnx Register performed on the next compare match. For compare output actions in the 8209D–AVR–11/10 Waveform Generator I/O for details. See “Register Description” on page 123. ATmega16M1/32M1/64M1 Figure 15 OCnx 0 D ...
Page 114
... The timing diagram for the CTC mode is shown in (TCNTn) increases until a compare match occurs with either OCRnA or ICRn, and then counter (TCNTn) is cleared. ATmega16M1/32M1/64M1 114 Table 15-5 on page 123. For fast PWM mode refer to “Timer/Counter Timing Diagrams” on page ...
Page 115
... OCRnA is set to zero (0x0000). The waveform frequency clk_I -------------------------------------------------- - ⋅ OCnA 2 N ATmega16M1/32M1/64M1 OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) (COMnA1 clk_I/O ⋅ OCRnA 115 ...
Page 116
... TOP value. The counter will then have to count to the MAX value (0xFFFF) and wrap around starting at 0x0000 before the compare match can occur. The OCRnA Register however, is double buffered. This feature allows the OCRnA I/O location ATmega16M1/32M1/64M1 116 ( ...
Page 117
... However, due to the symmetric feature of the dual-slope PWM modes, these modes are preferred for motor control applications. The PWM resolution for the phase correct PWM mode can be fixed to 8-bit, 9-bit, or 10-bit, or defined by either ICRn or OCRnA. The minimum resolution allowed is 2-bit (ICRn or OCRnA set 8209D–AVR–11/10 ATmega16M1/32M1/64M1 Table on page f clk_I/O f ...
Page 118
... TOP actively while the Timer/Counter is running in the phase correct mode can result in an unsymmetrical output. The reason for this can be found in the time of update of the OCRnx Reg- ister. Since the OCRnx update occurs at TOP, the PWM period starts and ends at TOP. This ATmega16M1/32M1/64M1 118 ( ...
Page 119
... The PWM resolution for the phase and frequency correct PWM mode can be defined by either ICRn or OCRnA. The minimum resolution allowed is 2-bit (ICRn or OCRnA set to 0x0003), and the maximum resolution is 16-bit (ICRn or OCRnA set to MAX). The PWM resolution in bits can be calculated using the following equation: 8209D–AVR–11/10 ATmega16M1/32M1/64M1 f OCnxPCPWM and Figure 15-9 on page 120) ...
Page 120
... TOP is clearly a better choice due to its double buffer feature. In phase and frequency correct PWM mode, the compare units allow generation of PWM wave- forms on the OCnx pins. Setting the COMnx1:0 bits to two will produce a non-inverted PWM and ATmega16M1/32M1/64M1 120 Figure 15-9. The figure shows phase and frequency correct ...
Page 121
... OCnxPFCPWM Figure 15-10 clk I/O clk Tn (clk /1) I/O TCNTn OCRnx - 1 OCRnx OCFnx shows the same timing data, but with the prescaler enabled. ATmega16M1/32M1/64M1 f clk_I/O = --------------------------- - ⋅ ⋅ TOP ) is therefore shown shows a timing diagram for the setting of OCFnx. OCRnx OCRnx + 1 OCRnx + 2 OCRnx Value Table 15-7 on ...
Page 122
... TOP should be replaced by BOTTOM, TOP-1 by BOTTOM+1 and so on. The same renaming applies for modes that set the TOVn Flag at BOTTOM. Figure 15-12. Timer/Counter Timing Diagram, no Prescaling (CTC and FPWM) (PC and PFC PWM) and ICFn Figure 15-13 on page 123 ATmega16M1/32M1/64M1 122 clk I/O clk Tn /8) ...
Page 123
... TOP COM1A1 COM1A0 COM1B1 R/W R/W R Table 15-5 Compare Output Mode, non-PWM COMnA0/COMnB0 ATmega16M1/32M1/64M1 /8) clk_I/O TOP BOTTOM TOP TOP - 1 New OCRnx Value COM1B0 – – WGM11 R R shows the COMnx1:0 bit functionality when the ...
Page 124
... Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare match (CTC) mode, and three types of Pulse Width Modulation (PWM) modes. PWM” on page 102. ATmega16M1/32M1/64M1 124 shows the COMnx1:0 bit functionality when the WGMn3:0 bits are set to the fast Compare Output Mode, Fast PWM ...
Page 125
... CTC 0 1 (Reserved Fast PWM 1 1 Fast PWM ICNC1 ICES1 RTGEN WGM13 R/W R ATmega16M1/32M1/64M1 Update of x TOP OCRn 0xFFFF Immediate 0x00FF TOP 0x01FF TOP 0x03FF TOP OCRnA Immediate 0x00FF TOP 0x01FF TOP 0x03FF TOP ICRn BOTTOM OCRnA BOTTOM ...
Page 126
... FOCnA/FOCnB bit, an immediate compare match is forced on the Waveform Generation unit. The OCnA/OCnB output is changed according to its COMnx1:0 bits setting. Note that the FOCnA/FOCnB bits are implemented as strobes. Therefore it is the value present in the COMnx1:0 bits that determine the effect of the forced compare. ATmega16M1/32M1/64M1 126 and Figure 15-11 on page 122 ...
Page 127
... The Output Compare Registers are 16-bit in size. To ensure that both the high and low bytes are written simultaneously when the CPU writes to these registers, the access is performed using an 8-bit temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit registers. 8209D–AVR–11/10 ATmega16M1/32M1/64M1 ...
Page 128
... R See “Accessing 16-bit Registers” on page 104 – – ICIE1 “Interrupt Vectors in ATmega16M1/32M1/64M1” on page “Interrupt Vectors in ATmega16M1/32M1/64M1” on page “Interrupt Vectors in ATmega16M1/32M1/64M1” on page ICR1[15:8] ICR1[7:0] R/W R/W R – – OCIE1B ...
Page 129
... TOV1 Flag is set when the timer overflows. Refer to Flag behavior when using another WGMn3:0 bit setting. TOV1 is automatically cleared when the Timer/Counter1 Overflow Interrupt Vector is executed. Alternatively, TOV1 can be cleared by writing a logic one to its bit location. 8209D–AVR–11/10 ATmega16M1/32M1/64M1 – ...
Page 130
... Tn clk I/O The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles from an edge has been applied to the Tn/T0 pin to the counter is updated. ATmega16M1/32M1/64M1 130 (see page 102) share the same prescaler module, but the Timer/Counters can have different ). Alternatively, one of four taps from the prescaler can be used as a ...
Page 131
... Figure 16-2. Prescaler for Timer/Counter0 and Timer/Counter1 clk I/O PSRSYNC T0 T1 Note: 8209D–AVR–11/10 < f /2) given a 50/50% duty cycle. Since the edge detector uses ExtClk clk_I/O Clear Synchronization Synchronization clk 1. The synchronization logic on the input pins (Tn) is shown in ATmega16M1/32M1/64M1 (1) T1 Figure 16-1 on page 130 /2.5. clk_I/O clk T0 131 ...
Page 132
... When this bit is one, Timer/Counter1 and Timer/Counter0 prescaler will be Reset. This bit is nor- mally cleared immediately by hardware, except if the TSM bit is set. Note that Timer/Counter1 and Timer/Counter0 share the same prescaler and a reset of this prescaler will affect both timers. ATmega16M1/32M1/64M1 132 7 6 ...
Page 133
... CPU, the high byte of the 16-bit register is copied into the temporary register in the same clock cycle as the low byte is read 16-bit write, the high byte must be written before the low byte. For a 16-bit read, the low byte must be read before the high byte. 8209D–AVR–11/10 ATmega16M1/32M1/64M1 133 ...
Page 134
... PSC Description Figure 17-1. Power Stage Controller Block Diagram ATmega16M1/32M1/64M1 134 PSC Counter POCR_RB = Waveform Generator B POCR0SB = Overlap Protection POCR0RA = Waveform Generator A = POCR0SA Waveform Generator B POCR1SB = Overlap Protection POCR1RA = Waveform Generator A POCR1SA = Waveform Generator B POCR2SB = Overlap Protection POCR2RA = Waveform Generator A POCR2SA = PSOCn ...
Page 135
... The PSC can be configured in one of two modes (1Ramp Mode or Centered Mode). This config- uration will affect the operation of all the waveform generators. Figure 17-2. Cycle Presentation in One Ramp Mode PSC Counter Value 8209D–AVR–11/10 ATmega16M1/32M1/64M1 Figure 17-1 on page One PSC Cycle Sub-Cycle A Sub-Cycle B ...
Page 136
... In this mode, the PWM frequency is twice slower than in One Ramp Mode 17.5.3.1 One Ramp Mode (Edge-Aligned) The following figure shows the resultant outputs PSCOUTnA and PSCOUTnB operating in one ramp mode over a PSC cycle. ATmega16M1/32M1/64M1 136 One PSC Cycle and Figure 17-3 graphically illustrate the values held in the PSC coun- UPDATE 8209D– ...
Page 137
... Figure 17-5. Controlled Start and Stop Mechanism in One-Ramp Mode POCRnRB POCRnSB POCRnRA POCRnSA PSC Counter Run PSCOUTnA PSCOUTnB Note: See “PCTL – PSC Control Register” on page 150. 8209D–AVR–11/10 POCRnSA 0 On-Time A Dead-Time A PSC Cycle Minimal value for Dead-Time A = 1/Fclkpsc 0 (PCCYC = 1) ATmega16M1/32M1/64M1 POCRnRB POCRnSB POCRnRA On-Time B Dead-Time B 137 ...
Page 138
... PSC Cycle = 2 × (POCRnRBH × 1/Fclkpsc Note: Note that in center aligned mode, POCRnRAH/L is not required ( one-ramp mode) to control PSC Output waveform timing. This allows POCRnRAH freely used to adjust ADC synchronization. ATmega16M1/32M1/64M1 138 PSC Counter On-Time 1 Dead-Time Minimal value for PSC Cycle = 2 × 1/Fclkpsc See “ ...
Page 139
... See these register’s description starting on 8209D–AVR–11/10 0 150.(PCCYC = 1) Regulation Loop Writting in Calculation PSC Registers Software Cycle Cycle Cycle With Set i With Set i With Set i PSC page ATmega16M1/32M1/64M1 Request for an Update Cycle With Set i Cycle With Set j End of Cycle 148. 139 ...
Page 140
... Overlap Protection Thanks to Overlap Protection two outputs on a same module cannot be active at the same time cannot generate cross conduction. This feature can be disactivated thanks to POVEn (PSC Overlap Enable). 17.8 Signal Description Figure 17-9. PSC External Block View ATmega16M1/32M1/64M1 140 CLK PLL CLK I/O 12 ...
Page 141
... PSC Module 1 Output A PSC Module 1 Output B PSC Module 2 Output A PSC Module 2 Output B Internal Outputs Description PSC Interrupt Request: two souces, overflow, fault ADC Synchronization (+ Amplifier Syncho See “Analog Synchronization” on page 145. ATmega16M1/32M1/64M1 (1) Type Width Register 12 bits Register 12 bits Register 12 bits ...
Page 142
... This way needs that CLK trol bit (PAOCnA/B), PSCINn input can desactivate directly the PSC outputs. Notice that in this case, input is still taken into account as usually by Input Module System as soon as CLK running. ATmega16M1/32M1/64M1 142 PSCINn input can act has a Retrigger or Fault input. PAOCnA ...
Page 143
... PSC Input Module X PSC Input Mode Operation Description No action, PSC Input is ignored Disactivate module n Outputs A Disactivate module n Output B Disactivate module n Output A & B Disactivate all PSC Output Halt PSC and Wait for Software Action ATmega16M1/32M1/64M1 PSC Module n Input Ouput PSCOUTnX Stage PIN 143 ...
Page 144
... Figure 17-14. PSC behaviour versus PSCn Input A in Fault Mode 11xb DT0 OT0 PSCOUTnA PSCOUTnB PSCn Input Note: 1. Software action is the setting of the PRUNn bit in PCTLn register Used in Fault mode 7, PSCn Input A or PSCn Input B act indifferently on On-Time0/Dead-Time0 or on On-Time1/Dead-Time1. ATmega16M1/32M1/64M1 144 DT1 OT1 DT0 OT0 DT1 DT1 OT1 DT0 ...
Page 145
... Figure 17-15. Clock selection PCLKSELn bit in PSC Control Register (PCTL) is used to select the clock source. PPREn1/0 bits in PSC Control Register (PCTL) are used to select the divide factor of the clock. Table 17-6. PCLKSELn 8209D–AVR–11/10 ATmega16M1/32M1/64M1 CLK 1 PLL CK CLK 0 I/O PCLKSEL Output Clock versus Selection and Prescaler ...
Page 146
... ATmega16M1/32M1/64M1. 17.15.1 Interrupt Vector PSC provides 2 interrupt vectors: • PSC_End (End of Cycle): When enabled and when a match with POCR_RB occurs • PSC_Fault (Fault Event): When enabled and when a PSC input detects a Fault event 17.15.2 PSC Interrupt Vectors in ATmega16M1/32M1/64M1 Table 17-7. Vector No ...
Page 147
... Select the polarity and signal source for generating a signal which will be sent from module 2 to the ADC for synchronization. • Bit 3:2 – PSYNC1[1:0]: Synchronization Out for ADC Selection Select the polarity and signal source for generating a signal which will be sent from module 1 to the ADC for synchronization. 8209D–AVR–11/10 ATmega16M1/32M1/64M1 ...
Page 148
... POCRnRAH and POCRnRAL – PSC Output Compare RA Register Bit Read/Write Initial Value 17.16.5 POCRnSBH and POCRnSBL – PSCOutput Compare SB Register Bit Read/Write Initial Value ATmega16M1/32M1/64M1 148 Synchronization Source Description in One Ramp Mode PSYNCn0 Description 0 Send signal on leading edge of PSCOUTnA(match with OCRnSA) Send signal on trailing edge of PSCOUTnA(match with OCRnRA or 1 ...
Page 149
... If this bit is set, the PSC outputs B are active High. • Bit 2 – POPA: PSC A Output Polarity If this bit is cleared, the PSC outputs A are active Low. If this bit is set, the PSC outputs A are active High. 8209D–AVR–11/10 ATmega16M1/32M1/64M1 – ...
Page 150
... The Input Control Registers are used to configure the 2 PSC’s Retrigger/Fault block A & B. The 2 blocks are identical, so they are configured on the same way. • Bit 7 – POVENn: PSC Module n Overlap Enable Set this bit to disactivate the Overlap Protection. See ATmega16M1/32M1/64M1 150 7 6 ...
Page 151
... These bits are reserved and will always read as zero. • Bit 3 – PEVE2: PSC External Event 2 Interrupt Enable When this bit is set, an external event which can generates a a fault on module 2 generates also an interrupt. 8209D–AVR–11/10 ATmega16M1/32M1/64M1 Description No action, PSC Input is ignored Disactivate module n Outputs A Disactivate module n Output B Disactivate module n Output A & ...
Page 152
... This bit can be read even if the corresponding interrupt is not enabled (PEVE0 bit = 0). • Bit 0 – PEOP: PSC End Of Cycle Interrupt This bit is set by hardware when an “end of PSC cycle” occurs. Must be cleared by software by writing a one to its location. This bit can be read even if the corresponding interrupt is not enabled (PEOPE bit = 0). ATmega16M1/32M1/64M1 152 ...
Page 153
... Wake-up from Idle Mode • Double Speed (CK/2) Master SPI Mode 18.2 Overview The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the ATmega16M1/32M1/64M1 and peripheral devices or between several AVR devices. Figure 18-1. SPI Block Diagram /2/4/8/16/32/64/128 Note: 8209D–AVR–11/10 (1) clk ...
Page 154
... SPI Data Register before the next character has been completely shifted in. Oth- erwise, the first byte is lost. In SPI Slave mode, the control logic will sample the incoming signal of the SCK pin. To ensure correct sampling of the clock signal, the frequency of the SPI clock should never exceed f ATmega16M1/32M1/64M1 154 Figure 18-2. The sys- ...
Page 155
... SPI Pin Overrides Direction, Master SPI User Defined Input User Defined User Defined 1. See “Alternate Functions of Port B” on page 70 direction of the user defined SPI pins ATmega16M1/32M1/64M1 Direction, Slave SPI Input User Defined Input Input for a detailed description of how to define the “Alternate Port 155 ...
Page 156
... Start transmission */ SPDR = cData; /* Wait for transmission complete */ while(!(SPSR & (1<<SPIF))) } Note: The following code examples show how to initialize the SPI as a Slave and how to perform a simple reception. ATmega16M1/32M1/64M1 156 (1) r17,(1<<DD_MOSI)|(1<<DD_SCK) DDR_SPI,r17 r17,(1<<SPE)|(1<<MSTR)|(1<<SPR0) SPCR,r17 SPDR,r16 (1) ...
Page 157
... Read received data and return in r16,SPDR ret (1) /* Set MISO output, all others input */ DDR_SPI = (1<<DD_MISO); /* Enable SPI */ SPCR = (1<<SPE); /* Wait for reception complete */ while(!(SPSR & (1<<SPIF))) ; /* Return data register */ return SPDR; 1. The example code assumes that the part specific header file is included ATmega16M1/32M1/64M1 157 ...
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... SCK signal, ensuring sufficient time for data signals to stabilize. This is clearly seen by summarizing below: Table 18-4. CPOL=0, CPHA=0 CPOL=0, CPHA=1 CPOL=1, CPHA=0 CPOL=1, CPHA=1 ATmega16M1/32M1/64M1 158 and Figure 18-4 on page 159. Data bits are shifted out and latched in on Table 18-5 on page 160 CPOL Functionality Leading Edge ...
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... MOSI PIN CHANGE 0 MISO PIN SS MSB first (DORD = 0) MSB Bit 6 LSB first (DORD = 1) LSB Bit SPIPS – – R ATmega16M1/32M1/64M1 Bit 4 Bit 3 Bit 2 Bit 1 Bit 3 Bit 4 Bit 5 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit ...
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... CPOL functionality is summarized below: Table 18-5. • Bit 2 – CPHA: Clock Phase The settings of the Clock Phase bit (CPHA) determine if data is sampled on the leading (first) or trailing (last) edge of SCK. Refer to example. The CPOL functionality is summarized below: Table 18-6. ATmega16M1/32M1/64M1 160 SPIE ...
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... When this bit is written logic one the SPI speed (SCK Frequency) will be doubled when the SPI is in Master mode (see clock periods. When the SPI is configured as Slave, the SPI is only guaranteed to work lower. The SPI interface on the ATmega16M1/32M1/64M1 is also used for program memory and EEPROM downloading or uploading. See programming and verification. 8209D–AVR–11/10 ...
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... Bits 7:0 - SPD7:0: SPI Data The SPI Data Register is a read/write register used for data transfer between the Register File and the SPI Shift Register. Writing to the register initiates data transmission. Reading the regis- ter causes the Shift Register Receive buffer to be read. ATmega16M1/32M1/64M1 162 7 6 ...
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... Overview The Controller Area Network (CAN) protocol is a real-time, serial, broadcast protocol with a very high level of security. The ATmega16M1/32M1/64M1 CAN controller is fully compatible with the CAN Specification 2.0 Part A and Part B. It delivers the features required to implement the ker- nel of the CAN bus protocol according to the ISO/OSI Reference Model: • ...
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... The end of the message is indicated by "End Of Frame (EOF)". The "Intermission Frame Space (IFS)" is the minimum number of bits separating consecutive messages. If there is no following bus access by any node, the bus remains idle. ATmega16M1/32M1/64M1 164 4-bit DLC 15-bit CRC bytes DLC4 ...
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... DLC RTR r1 r0 ID17..0 DLC4..0 Control Field 18-bit identifier extension 4-bit DLC RTR r1 r0 15-bit CRC ID17..0 DLC4..0 Control Field ATmega16M1/32M1/64M1 CRC ACK 15-bit CRC ACK 7 bits bytes del. del. Data CRC ACK End of Field Field Field Frame CRC ...
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... The IPT begins at the sample point, is measured in TQ and is fixed at 2TQ for the Atmel CAN. Since Phase Segment 2 also begins at the sample point and is the last segment in the bit time, PS2 minimum shall not be less than the IPT. ATmega16M1/32M1/64M1 166 Nominal CAN Bit Time ...
Page 167
... The bus access conflict is resolved during the arbitration field mostly over the identifier value data frame and a remote frame with the same identifier are initiated at the same time, the data frame prevails over the remote frame (c.f. RTR bit). 8209D–AVR–11/10 ATmega16M1/32M1/64M1 167 ...
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... This prevents other nodes accepting the message and thus ensures the consistency of data throughout the network. After transmission of an erroneous message that has been aborted, the sender automatically re-attempts transmission. ATmega16M1/32M1/64M1 168 node A TXCAN node B ...
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... CAN Controller The CAN controller implemented into ATmega16M1/32M1/64M1 offers V2.0B Active. This full-CAN controller provides the whole hardware for convenient acceptance filtering and message management. For each message to be transmitted or received this module contains one so called message object in which all information regarding the message (for example iden- tifier, data bytes etc ...
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... PHS1: PHase Segment 1 is programmable ..., 8 TQ long • PHS2: PHase Segment 2 is programmable to be ≤ PHS1 and ≥ INFORMATION PROCESSING TIME • INFORMATION PROCESSING TIME • SJW: (Re) Synchronization Jump Width is programmable between 1 and min (4, PHS1) ATmega16M1/32M1/64M1 170 receiver is disabled internal TxCAN ...
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... Bit Timing PRS (3-bit length) PHS1 (3-bit length) Fcan (Tscl) Time Quantum PHS2 (3-bit length) SJW (2-bit length CLK IO Bit Rate Prescaler Tscl (TQ) one nominal bit Tsyns(5) Tprs Tbit ATmega16M1/32M1/64M1 Sample Point Transmission Point Tphs1 ( ) Tphs2 ( ) Tphs1+Tsjw ( ) ...
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... Disabled mode – Transmit mode – Receive mode – Automatic reply – Frame buffer receive mode ATmega16M1/32M1/64M1 172 (1) Tbit = Tsyns + Tprs + Tphs1 + Tphs2 1. The total number of Tscl (Time Quanta bit time must be from PHS2[2.. programmable to be Setting OVRQ bit Ident " ...
Page 173
... Identifier extension (IDE) – Identifier extension mask (IDEMSK) – Remote transmission request (RTRTAG) – Remote transmission request mask (RTRMSK) – Data length code (DLC) – Reserved bit(s) tag (RBnTAG) 8209D–AVR–11/10 ATmega16M1/32M1/64M1 MOb Configuration Reply Valid RTR Tag ...
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... BXOK flag is set (interrupt). BXOK flag can be cleared only if all CONMOB fields of the set have been re-written before 7. All the parameters and data are available in the MObs until a new initialization ATmega16M1/32M1/64M1 174 Data & Remote Frame” on page 173 Section 19.6.2.3 “Rx ...
Page 175
... ID MSK = 111 1111 1000 TAG = 011 0001 0xxx b No filtering: to accept all ID’s from 0x000 up to 0x7FF in part MSK = 000 0000 0000 TAG = xxx xxxx xxxx b Figure 19-14 on page 179). ATmega16M1/32M1/64M1 IDE RB excluded = 13(31) 1 13(31) IDMSK RTRMSK CANIDM Registers (MOb[i]) Hit MOb[i] ...
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... In TTC mode, a frame is sent once, even if an error occurs. 19.7.4 Stamping Message The capture of the timer value is done in the MOb which receives or sends the frame. All man- aged MOb are stamped, the stamping of a received (sent) frame occurs on RxOk (TXOK). ATmega16M1/32M1/64M1 176 CANTCON 8 clk ...
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... More than one REC/TEC change may apply during a given message transfer Exceptions: - Recessive bit sent monitored as dominant bit during the arbitration field and the acknowl- edge slot - Detecting a dominant bit during the sending of an error frame ATmega16M1/32M1/64M1 Reset Error Active 128 occurrences ...
Page 178
... Interrupt on frame buffer full • Interrupt on “Bus Off” setting • Interrupt on overrun of CAN timer The general interrupt enable is provided by ENIT bit and the specific interrupt enable for CAN timer overrun is provided by ENORVT bit. ATmega16M1/32M1/64M1 178 Arbitration SOF Identifier RTR ...
Page 179
... When a MOb error occurs and is set in its own CANSTMOB register, no general error is set in CANGIT register. 8209D–AVR–11/10 CANGIE.5 CANGIE.3 ENRX ENERR CANSIT 1/2 SIT[i] CANIE 1/2 CANGIE.2 CANGIE.1 CANGIE.6 ENBX ENERG ENBOFF ATmega16M1/32M1/64M1 IEMOB[i] 0 CANGIT.7 CANIT i CANGIE.7 CANGIE.0 ENOVRT ENIT CAN IT OVR IT 179 ...
Page 180
... ID Tag 2 ID Tag 1 ID Mask 4 ID Mask 3 ID Mask 2 ID Mask 1 Time Stamp Low Time Stamp High Message Data 8 bytes ATmega16M1/32M1/64M1 180 Registers in Pages MOb0 - MOb Status MOb0 - MOb Ctrl & DLC MOb0 - ID Tag 4 MOb0 - ID Tag 3 MOb0 - ID Tag 2 MOb0 - ID Tag 1 MOb0 - ID Mask 4 ...
Page 181
... ABRQ OVRQ TTC R/W R/W R communications are immediately disabled and the on-going one will be normally terminated, setting the appropriate status flags Note that CANCDMOB register remain unchanged CAN may malfunction if this bit is set ATmega16M1/32M1/64M1 SYNTTC LISTEN TEST ENA/STB R/W R/W R/W R ...
Page 182
... This flag does not generate an interrupt. – receiver not busy – receiver busy: set by hardware as long as a frame is received or monitored ATmega16M1/32M1/64M1 182 CAN channel is frozen (the CONMOB bits of every MOb do not change). The transmitter constantly provides a recessive level. In this mode, the receiver is not enabled but all the registers and mailbox remain accessible from CPU ...
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... MOb’s of the buffer have been re-written before. 8209D–AVR–11/10 effective, this status gives the true state of the chosen mode CANIT BOFFIT OVRTIM R R/W R interrupt. This bit can be used for polling method ATmega16M1/32M1/64M1 BXOK SERG CERG FERG R/W R/W R/W R ...
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... CANIT interrupt enabled • Bit 6 – ENBOFF: Enable Bus Off Interrupt – interrupt disabled – 1- bus off interrupt enabled • Bit 5 – ENRX: Enable Receive Interrupt – interrupt disabled – 1- receive interrupt enabled ATmega16M1/32M1/64M1 184 polarity CRC field acknowledgment delimiter or EOF slot 7 ...
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... ENMOB is also set to zero configuring the MOb in disabled mode, applying abortion or standby mode. – message object disabled: MOb available for a new transmission or reception – message object enabled: MOb in use • Bit 15:6 – Res: Reserved These bits are reserved and will always read as zero. 8209D–AVR–11/10 ATmega16M1/32M1/64M1 ...
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... These bits are reserved and will always read as zero. 19.10.8 CANBT1 – CAN Bit Timing Register 1 Bit Read/Write Initial Value • Bit 7– Res: Reserved This bit is reserved for future use. For compatibility with future devices, it must be written to zero when CANBT1 is written. ATmega16M1/32M1/64M1 186 IEMOB5 IEMOB4 ...
Page 187
... Bit 0 – Res: Reserved This bit is reserved for future use. For compatibility with future devices, it must be written to zero when CANBT2 is written. 8209D–AVR–11/10 ATmega16M1/32M1/64M1 BRP[5: Tscl = clk Section 19.5.3 “Baud Rate” on page 172 188. ...
Page 188
... CANTCON – CAN Timer Control Register Bit Read/Write Initial Value • Bit 7:0 – TPRSC[7:0]: CAN Timer Prescaler Prescaler for the CAN timer upper counter range 0 to 255. It provides the clock to the CAN timer if the CAN controller is enabled. T clk CANTIM ATmega16M1/32M1/64M1 188 PHS22 PHS21 - R/W ...
Page 189
... REC7 REC6 REC5 HPMOB3 HPMOB2 HPMOB1 HPMOB0 not confuse “MOb priority” and “Message ID priority”- ATmega16M1/32M1/64M1 CANTIM3 CANTIM2 CANTIM1 CANTIM11 CANTIM10 CANTIM9 ...
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... This flag can generate an interrupt. It must be cleared using a read-modify-write software routine on the whole CANSTMOB register. The communication enabled by reception is completed. RxOK rises at the end of the 6 EOF field. In case of two or more message object reception hits, the lower MOb index (0 to 14) is updated first. ATmega16M1/32M1/64M1 190 ...
Page 191
... Initial Value • Bit 7:6 – CONMOB[1:0]: Configuration of Message Object These bits set the communication to be performed (no initial value after RESET). – disable – enable transmission – enable reception – enable frame buffer reception 8209D–AVR–11/10 ATmega16M1/32M1/64M1 CONMOB1 CONMOB0 RPLV ...
Page 192
... This field is updated with the corresponding value of the remote or data frame received. If the expected DLC differs from the incoming DLC, a DLC warning appears in the CANSTMOB register. 19.11.3 CANIDT1, CANIDT2, CANIDT3, and CANIDT4 – CAN Identifier Tag Registers V2.0 part A Bit Bit Read/Write Initial Value V2.0 part B Bit Bit Read/Write Initial Value ATmega16M1/32M1/64M1 192 15/7 14/6 13/5 12 IDT2 ...
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... This tag is updated with the corresponding value of the remote or data frame received. • Bit 0 – RB0TAG: Reserved Bit 0 Tag RB0 bit of the remote or data frame to send. This tag is updated with the corresponding value of the remote or data frame received. 8209D–AVR–11/10 ATmega16M1/32M1/64M1 193 ...
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... This bit is reserved for future use. For compatibility with future devices, it must be written to zero when CANIDTn are written. • Bit 0 – IDEMSK: Identifier Extension Mask – comparison true forced – bit comparison enabled V2.0 part B • Bit 31:3 – IDMSK[28:0]: Identifier Mask – comparison true forced - – bit comparison enabled. - ATmega16M1/32M1/64M1 194 15/7 14/6 13/5 12 ...
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... TIMSTM15 TIMSTM14 TIMSTM13 TIMSTM12 TIMSTM11 TIMSTM10 MSG 7 MSG 6 MSG 5 MSG 4 R/W R/W R “Bit Timing” on page 170 and “Baud Rate” on page 172 for “CAN Bit Timing Registers”). ATmega16M1/32M1/64M1 TIMSTM3 TIMSTM2 TIMSTM1 TIMSTM9 MSG 3 MSG 2 ...
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... Sampling CLK IO (MHz) (Kbps) Point ( 1000 75 % 500 75 % 250 75 % 16.000 200 75 % 125 75 % 100 75 % (1) 1000 67 % 500 75 % 250 75 % 12.000 200 75 % 125 75 % 100 75 % ATmega16M1/32M1/64M1 196 Segments TQ Tbit Tprs Tph1 (µs) (TQ) (TQ) (TQ) 0.0625 0.125 0.125 0.250 0.250 0.500 ...
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... ATmega16M1/32M1/64M1 Registers Tph2 Tsjw (TQ) (TQ) CANBT1 CANBT2 - - - 0x00 0x04 4 1 0x00 0x0C 2 1 0x02 0x04 4 1 0x02 0x0C 2 1 0x06 0x04 5 ...
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... LIN provides a cost efficient bus communication where the bandwidth and versatility of CAN are not required. The specification of the line driver/receiver needs to match the ISO9141 NRZ- standard. If LIN is not required, the controller alternatively can be programmed as Universal Asynchronous serial Receiver and Transmitter (UART). ATmega16M1/32M1/64M1 198 8209D–AVR–11/10 ...
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... LIN bus HEADER RESPONSE FRAME SLOT PROTECTED IDENTIFIER DATA-0 Field Field Response Space ATmega16M1/32M1/64M1 slave node 1 n slave task HEADER RESPONSE DATA-n CHECKSUM Field Field Inter-Byte Space Each byte field is transmitted as a serial byte, LSB first. ...
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... Because these two services are basically UART services, the controller is also able to switch into an UART function. 20.4.1 LIN Overview The LIN/UART controller is designed to match as closely as possible to the LIN software appli- cation structure. The LIN software application is developed as independent tasks, several slave ATmega16M1/32M1/64M1 200 8209D–AVR–11/10 ...