ATmega16M1 Atmel Corporation, ATmega16M1 Datasheet - Page 20
ATmega16M1
Manufacturer Part Number
ATmega16M1
Description
Manufacturer
Atmel Corporation
Specifications of ATmega16M1
Flash (kbytes)
16 Kbytes
Pin Count
32
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
12
Hardware Qtouch Acquisition
No
Max I/o Pins
27
Ext Interrupts
27
Usb Speed
No
Usb Interface
No
Spi
1
Uart
1
Can
1
Lin
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
11
Adc Resolution (bits)
10
Adc Speed (ksps)
125
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
1
Dac Resolution (bits)
10
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
1
Eeprom (bytes)
512
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
2
Output Compare Channels
14
Input Capture Channels
1
Pwm Channels
10
32khz Rtc
No
Calibrated Rc Oscillator
Yes
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7.4
7.4.1
20
EEPROM Data Memory
ATmega16M1/32M1/64M1
EEPROM Read/Write Access
Figure 7-3.
The ATmega16M1/32M1/64M1 contains 512B/1K/2K bytes of data EEPROM memory. It is
organized as a separate data space, in which single bytes can be read and written. The
EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the
EEPROM and the CPU is described in the following, specifying the EEPROM Address Regis-
ters, the EEPROM Data Register, and the EEPROM Control Register.
For a detailed description of SPI and Parallel data downloading to the EEPROM, see
Downloading” on page 302
mands” on page 291
The EEPROM Access Registers are accessible in the I/O space.
The write access time for the EEPROM is given in
however, lets the user software detect when the next byte can be written. If the user code con-
tains instructions that write the EEPROM, some precautions must be taken. In heavily filtered
power supplies, V
some period of time to run at a voltage lower than specified as minimum for the clock frequency
used.
these situations.
In order to prevent unintentional EEPROM writes, a specific write procedure must be followed.
Refer to the description of the EEPROM Control Register for details on this.
When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is
executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next
instruction is executed.
See “Preventing EEPROM Corruption” on page 21
On-chip Data SRAM Access Cycles
Address
CC
clk
Data
Data
WR
is likely to rise or fall slowly on power-up/down. This causes the device for
CPU
RD
respectively.
, and
Compute Address
“Parallel Programming Parameters, Pin Mapping, and Com-
T1
Memory Access Instruction
Table 7-2 on page
Address valid
T2
for details on how to avoid problems in
Next Instruction
24. A self-timing function,
T3
8209D–AVR–11/10
“Serial
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