ATmega16 Atmel Corporation, ATmega16 Datasheet - Page 178
![no-image](/images/manufacturer_photos/0/0/79/atmel_corporation_sml.jpg)
ATmega16
Manufacturer Part Number
ATmega16
Description
Manufacturer
Atmel Corporation
Specifications of ATmega16
Flash (kbytes)
16 Kbytes
Pin Count
44
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
32
Ext Interrupts
3
Usb Speed
No
Usb Interface
No
Spi
1
Twi (i2c)
1
Uart
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
1
Eeprom (bytes)
512
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
4
Input Capture Channels
1
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEGA16
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Part Number:
ATmega16-16AI
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Company:
Part Number:
ATmega16-16AU
Manufacturer:
ATMEL
Quantity:
537
Part Number:
ATmega16-16AU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Company:
Part Number:
ATmega16-16AUR
Manufacturer:
Encoders
Quantity:
101
Company:
Part Number:
ATmega16-16PC
Manufacturer:
ATM
Quantity:
100
Company:
Part Number:
ATmega16-16PI
Manufacturer:
RFMD
Quantity:
101
Company:
Part Number:
ATmega16-16PU
Manufacturer:
Atmel
Quantity:
140
Overview of the
TWI Module
SCL and SDA Pins
Bit Rate Generator
Unit
Bus Interface Unit
2466T–AVR–07/10
The TWI module is comprised of several submodules, as shown in
in a thick line are accessible through the AVR data bus.
Figure 84. Overview of the TWI Module
These pins interface the AVR TWI with the rest of the MCU system. The output drivers contain a
slew-rate limiter in order to conform to the TWI specification. The input stages contain a spike
suppression unit removing spikes shorter than 50 ns. Note that the internal pull-ups in the AVR
pads can be enabled by setting the PORT bits corresponding to the SCL and SDA pins, as
explained in the I/O Port section. The internal pull-ups can in some systems eliminate the need
for external ones.
This unit controls the period of SCL when operating in a Master mode. The SCL period is con-
trolled by settings in the TWI Bit Rate Register (TWBR) and the Prescaler bits in the TWI Status
Register (TWSR). Slave operation does not depend on Bit Rate or Prescaler settings, but the
CPU clock frequency in the Slave must be at least 16 times higher than the SCL frequency. Note
that Slaves may prolong the SCL low period, thereby reducing the average TWI bus clock
period. The SCL frequency is generated according to the following equation:
•
•
Note:
This unit contains the Data and Address Shift Register (TWDR), a START/STOP Controller and
Arbitration detection hardware. The TWDR contains the address or data bytes to be transmitted,
TWBR = Value of the TWI Bit Rate Register
TWPS = Value of the prescaler bits in the TWI Status Register
Note: Pull-up resistor values should be selected according to the SCL frequency and the capaci-
tive bus line load. See
Slew-rate
Address Match Unit
Arbitration detection
Control
START / STOP
Address Comparator
Address Register
Control
SCL
(TWAR)
Spike
Filter
Bus Interface Unit
SCL frequency
Table 120 on page 294
Spike Suppression
Address/Data Shift
Register (TWDR)
Slew-rate
Control
=
SDA
Status Register
---------------------------------------------------------- -
16
CPU Clock frequency
Ack
Spike
Filter
(TWSR)
+
for value of pull-up resistor.
2(TWBR) 4
State Machine and
Control Unit
Status control
⋅
TWPS
Control Register
Bit Rate Generator
(TWCR)
Figure
Bit Rate Register
Prescaler
ATmega16(L)
(TWBR)
84. All registers drawn
TWI Unit
178