ATmega128RZAV Atmel Corporation, ATmega128RZAV Datasheet - Page 239
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ATmega128RZAV
Manufacturer Part Number
ATmega128RZAV
Description
Manufacturer
Atmel Corporation
Specifications of ATmega128RZAV
Flash (kbytes)
128 Kbytes
Max. Operating Frequency
16 MHz
Max I/o Pins
54
Spi
3
Twi (i2c)
1
Uart
2
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Crypto Engine
No
Sram (kbytes)
8
Eeprom (bytes)
4096
Operating Voltage (vcc)
1.8 to 3.6
Timers
6
Frequency Band
2.4 GHz
Max Data Rate (mb/s)
0.25
Antenna Diversity
No
External Pa Control
No
Power Output (dbm)
3
Receiver Sensitivity (dbm)
-101
Receive Current Consumption (ma)
16.0
Transmit Current Consumption (ma)
17.0
Link Budget (dbm)
104
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23.6.4
2549N–AVR–05/11
UCSRnC – USART MSPIM Control and Status Register n C
• Bit 5 - UDRIE: USART Data Register Empty Interrupt Enable
Writing this bit to one enables interrupt on the UDREn Flag. A Data Register Empty interrupt will
be generated only if the UDRIE bit is written to one, the Global Interrupt Flag in SREG is written
to one and the UDREn bit in UCSRnA is set.
• Bit 4 - RXENn: Receiver Enable
Writing this bit to one enables the USART Receiver in MSPIM mode. The Receiver will override
normal port operation for the RxDn pin when enabled. Disabling the Receiver will flush the
receive buffer. Only enabling the receiver in MSPI mode (that is, setting RXENn=1 and
TXENn=0) has no meaning since it is the transmitter that controls the transfer clock and since
only master mode is supported.
• Bit 3 - TXENn: Transmitter Enable
Writing this bit to one enables the USART Transmitter. The Transmitter will override normal port
operation for the TxDn pin when enabled. The disabling of the Transmitter (writing TXENn to
zero) will not become effective until ongoing and pending transmissions are completed, that is,
when the Transmit Shift Register and Transmit Buffer Register do not contain data to be trans-
mitted. When disabled, the Transmitter will no longer override the TxDn port.
• Bit 2:0 - Reserved Bits in MSPI mode
When in MSPI mode, these bits are reserved for future use. For compatibility with future devices,
these bits must be written to zero when UCSRnB is written.
• Bit 7:6 - UMSELn1:0: USART Mode Select
These bits select the mode of operation of the USART as shown in
USART Control and Status Register n C” on page 225
operation. The MSPIM is enabled when both UMSELn bits are set to one. The UDORDn,
UCPHAn, and UCPOLn can be set in the same write operation where the MSPIM is enabled.
Table 23-3.
• Bit 5:3 - Reserved Bits in MSPI mode
When in MSPI mode, these bits are reserved for future use. For compatibility with future devices,
these bits must be written to zero when UCSRnC is written.
Bit
Read/Write
Initial Value
UMSELn1
0
0
1
1
UMSELn Bits Settings
UMSELn1
R/W
7
0
UMSELn0
R/W
6
0
UMSELn0
ATmega640/1280/1281/2560/2561
1
0
1
0
R
5
0
-
R
4
0
-
R
3
0
-
for full description of the normal USART
UDORDn
R/W
2
1
Asynchronous USART
Synchronous USART
Master SPI (MSPIM)
(Reserved)
Table
UCPHAn
Mode
R/W
1
1
23-3. See
UCPOLn
R/W
0
0
“UCSRnC –
UCSRnC
239
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