ATmega128RZAV Atmel Corporation, ATmega128RZAV Datasheet
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ATmega128RZAV
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ATmega128RZAV Summary of contents
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Features • ® High Performance, Low Power Atmel • Advanced RISC Architecture – 135 Powerful Instructions – Most Single Clock Cycle Execution – 32 × 8 General Purpose Working Registers – Fully Static Operation – MIPS Throughput ...
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Pin Configurations Figure 1-1. TQFP-pinout ATmega640/1280/2560 100 (OC0B) PG5 1 (RXD0/PCINT8) PE0 2 (TXD0) PE1 ...
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Figure 1-2. CBGA-pinout ATmega640/1280/2560 Top view Table 1- Note: 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 ...
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Figure 1-3. Pinout ATmega1281/2561 1 (OC0B) PG5 2 (RXD0/PCINT8/PDI) PE0 3 (TXD0/PDO) PE1 4 (XCK0/AIN0) PE2 5 (OC3A/AIN1) PE3 6 (OC3B/INT4) PE4 7 (OC3C/INT5) PE5 8 (T3/INT6) PE6 9 (ICP3/CLKO/INT7) PE7 10 (SS/PCINT0) PB0 11 (SCK/ PCINT1) PB1 12 (MOSI/ ...
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Overview The ATmega640/1280/1281/2560/2561 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega640/1280/1281/2560/2561 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to ...
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The Atmel ters. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while ...
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Comparison Between ATmega1281/2561 and ATmega640/1280/2560 Each device in the ATmega640/1280/1281/2560/2561 family differs only in memory size and number of pins. Table 2-1. Configuration Summary Device Flash EEPROM ATmega640 64KB ATmega1280 128KB ATmega1281 128KB ATmega2560 256KB ATmega2561 256KB 2.3 Pin ...
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The Port C pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port C also serves the functions of special features of the ATmega640/1280/1281/2560/2561 as listed on 2.3.6 Port D ...
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The Port H pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port H also serves the functions of various special features of the ATmega640/1280/2560 as listed on 2.3.11 Port ...
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AVCC AVCC is the supply voltage pin for Port F and the A/D Converter. It should be externally con- nected to V through a low-pass filter. 2.3.18 AREF This is the analog reference pin for the A/D Converter. 2549N–AVR–05/11 ...
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Resources A comprehensive set of development tools and application notes, and datasheets are available for download on http://www.atmel.com/avr. 4. About Code Examples This documentation contains simple code examples that briefly show how to use various parts of the device. ...
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AVR CPU Core 7.1 Introduction This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control ...
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The fast-access Register File contains 32 × 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation typ- ical ALU operation, two operands are output from the Register ...
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Status Register The Status Register contains information about the result of the most recently executed arithme- tic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the Status Register is ...
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Bit 1 – Z: Zero Flag The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the Set Summary” on page 416 • Bit 0 – C: Carry Flag The Carry Flag C indicates ...
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Figure 7-3. X-register Y-register Z-register In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see the for details). 7.6 Stack Pointer The Stack is mainly used for storing temporary data, for ...
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RAMPZ – Extended Z-pointer Register for ELPM/SPM Bit 0x3B (0x5B) Read/Write Initial Value For ELPM/SPM instructions, the Z-pointer is a concatenation of RAMPZ, ZH, and ZL, as shown in Figure 7-4. Figure 7-4. Bit ( Individually) Bit (Z-pointer) The ...
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Figure 7-6. 1st Instruction Execute 2nd Instruction Execute 3rd Instruction Execute Figure 7-7 operation using two register operands is executed, and the result is stored back to the destina- tion register. Figure 7-7. Register Operands Fetch ALU Operation Execute 7.8 ...
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There are basically two types of interrupts. The first type is triggered by an event that sets the Interrupt Flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vec- tor in order to execute the interrupt ...
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Assembly Code Example sei sleep; enter sleep, waiting for interrupt ; note: will enter sleep before any pending ; interrupt(s) C Code Example __enable_interrupt(); /* set Global Interrupt Enable */ __sleep(); /* enter sleep, waiting for interrupt */ /* note: ...
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AVR Memories This section describes the different memories in the ATmega640/1280/1281/2560/2561. The AVR architecture has two main memory spaces, the Data Memory and the Program Memory space. In addition, the ATmega640/1280/1281/2560/2561 features an EEPROM Memory for data storage. All ...
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An optional external data SRAM can be used with the ATmega640/1280/1281/2560/2561. This SRAM will occupy an area in the remaining address locations in the 64K address space. This area starts at the address following the internal SRAM. The Register file, ...
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Figure 8-2. 8.2.1 Data Memory Access Times This section describes the general access timing concepts for internal memory access. The internal data SRAM access is performed in two clk Figure 8-3. 8.3 EEPROM Data Memory The ATmega640/1280/1281/2560/2561 contains 4Kbytes of ...
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EEPROM Read/Write Access The EEPROM Access Registers are accessible in the I/O space, see page 35. The write access time for the EEPROM is given in lets the user software detect when the next byte can be written. If ...
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Assembly Code Example EEPROM_write: C Code Example void EEPROM_write(unsigned int uiAddress, unsigned char ucData Note: 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 (1) ; Wait for completion of previous write sbic EECR,EEPE rjmp EEPROM_write ; Set up address (r18:r17) in address register out ...
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The next code examples show assembly and C functions for reading the EEPROM. The exam- ples assume that interrupts are controlled so that no interrupts will occur during execution of these functions. Assembly Code Example EEPROM_read: C Code Example unsigned ...
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I/O Memory The I/O space definition of the ATmega640/1280/1281/2560/2561 is shown in mary” on page All ATmega640/1280/1281/2560/2561 I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring ...
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External Memory Interface With all the features the External Memory Interface provides well suited to operate as an interface to memory devices such as External SRAM and Flash, and peripherals such as LCD- display, A/D, and D/A. ...
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Using the External Memory Interface The interface consists of: • AD7:0: Multiplexed low-order address bus and data bus • ALE: Address latch enable • RD: Read strobe • WR: Write strobe The control bits for the External Memory Interface ...
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Figure 9-2. 9.1.3 Pull-up and Bus-keeper The pull-ups on the AD7:0 ports may be activated if the corresponding Port register is written to one. To reduce power consumption in sleep mode recommended to disable the pull-ups by writing ...
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Figure 9-3. System Clock (CLK Note: Figure 9-4. System Clock (CLK Note: 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 External Data Memory Cycles without Wait-state (SRWn1=0 and SRWn0= CPU ALE A15:8 Prev. addr. DA7:0 Prev. data WR DA7:0 (XMBK = 0) Prev. data ...
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Figure 9-5. System Clock (CLK Note: Figure 9-6. System Clock (CLK DA7:0 (XMBK = 0) DA7:0 (XMBK = 1) Note: 9.1.5 Using all Locations of External Memory Smaller than 64Kbytes Since the external memory is mapped after the internal memory ...
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Application software, the external 32Kbytes memory will appear as one linear 32Kbytes address space from 0x2200 to 0xA1FF. This is illustrated in Figure 9-7. 9.1.6 Using all 64Kbytes Locations of External Memory Since the External Memory is mapped after ...
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Assembly Code Example C Code Example #define OFFSET 0x4000 void XRAM_example(void Note: 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 (1) ; OFFSET is defined to 0x4000 to ensure ; external memory access ; Configure Port C (address high byte output 0x00 ...
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Register Description 9.2.1 EEPROM registers 9.2.1.1 EEARH and EEARL – The EEPROM Address Register Bit 0x22 (0x42) 0x21 (0x41) Read/Write Initial Value • Bits 15:12 – Res: Reserved Bits These bits are reserved bits and will always read as ...
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Table 9-1. EEPM1 • Bit 3 – EERIE: EEPROM Ready Interrupt Enable Writing EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set. Writing EERIE to zero disables the interrupt. ...
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Bit 0 – EERE: EEPROM Read Enable The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct address is set up in the EEAR Register, the EERE bit must be written to a ...
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Figure 9-1 on page external memory address space is treated as one sector. When the entire SRAM address space is configured as one sector, the wait-states are configured by the SRW11 and SRW10 bits. Table 9-2. SRL2 ...
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Bit 7– XMBK: External Memory Bus-keeper Enable Writing XMBK to one enables the bus keeper on the AD7:0 lines. When the bus keeper is enabled, AD7:0 will keep the last driven value on the lines even if the XMEM ...
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System Clock and Clock Options This section describes the clock options for the AVR microcontroller. 10.1 Overview Figure 10-1 clocks need not be active at a given time. In order to reduce power consumption, the clocks to modules not ...
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I/O Clock – clk I/O The I/O clock is used by the majority of the I/O modules, like Timer/Counters, SPI, and USART. The I/O clock is also used by the External Interrupt module, but note that some external inter- ...
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Default Clock Source The device is shipped with internal RC oscillator at 8.0MHz and with the fuse CKDIV8 pro- grammed, resulting in 1.0MHz system clock. The startup time is set to maximum and time-out period enabled. (CKSEL = "0010", ...
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C1 and C2 should always be equal for both crystals and resonators. The optimal value of the capacitors depends on the crystal or resonator in use, the amount of stray capacitance, and the electromagnetic noise of the environment. Some initial ...
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Table 10-4. Oscillator Source / Power Conditions Ceramic resonator, fast Ceramic resonator, slowly Crystal Oscillator, BOD enabled Crystal Oscillator, fast rising power Crystal Oscillator, slowly rising power Notes: 10.5 Full Swing Crystal Oscillator Pins XTAL1 and XTAL2 are input and ...
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Table 10-6. Oscillator Source / Power Conditions Ceramic resonator, fast Ceramic resonator, slowly Ceramic resonator, BOD Ceramic resonator, fast Ceramic resonator, slowly Crystal Oscillator, BOD Crystal Oscillator, fast Crystal Oscillator, slowly Notes: 10.6 Low Frequency Crystal Oscillator The device can ...
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The capacitance (Ce + Ci) needed at each XTAL/TOSC pin can be calculated by using: where optional external capacitors as described the pin capacitance the load capacitance for ...
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This clock may be selected as the system clock by programming the CKSEL Fuses as shown in Table 10-9. If selected, it will operate with no external components. During reset, hardware loads the pre-programmed calibration value into the OSCCAL Register ...
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When this clock source is selected, start-up times are determined by the SUT Fuses as shown in Table 10-12. Table 10-12. Start-up Times for the 128kHz Internal Oscillator Power Conditions Fast rising power Slowly rising power 10.9 External Clock To ...
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Note that the System Clock Prescaler can be used to implement run-time changes of the internal clock frequency while still ensuring stable operation. Refer to details. 10.10 Clock Output Buffer The device can output the system clock on the CLKO ...
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Register Description 10.13.1 OSCCAL – Oscillator Calibration Register Bit (0x66) Read/Write Initial Value • Bits 7:0 – CAL7:0: Oscillator Calibration Value The Oscillator Calibration Register is used to trim the Calibrated Internal RC Oscillator to remove process variations from ...
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Note that any value can be written to the CLKPS bits regardless of the CKDIV8 Fuse setting. The Application software must ensure ...
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Power Management and Sleep Modes Sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR provides various sleep modes allowing the user to tailor the power consump- tion to the application’s ...
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Idle mode enables the MCU to wake up from external triggered interrupts as well as internal ones like the Timer Overflow and USART Transmit Complete interrupts. If wake-up from the Analog Comparator interrupt is not required, the Analog Comparator can ...
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If the Timer/Counter2 is not using the synchronous clock, the clock source is stopped during sleep. Note that even if the synchronous clock is running in Power-save, this clock is only available for the Timer/Counter2. 11.6 Standby ...
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Internal Voltage Reference as input, the Analog Comparator should be disabled in all sleep modes. Otherwise, the Internal Voltage Reference will be enabled, independent of sleep mode. Refer to log Comparator. 11.9.3 Brown-out Detector If the Brown-out ...
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There are three alternative ways to disable the OCD system: • Disable the OCDEN Fuse • Disable the JTAGEN Fuse • Write one to the JTD bit in MCUCR 11.10 Register Description 11.10.1 SMCR – Sleep Mode Control Register The ...
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Bit 6 - PRTIM2: Power Reduction Timer/Counter2 Writing a logic one to this bit shuts down the Timer/Counter2 module in synchronous mode (AS2 is 0). When the Timer/Counter2 is enabled, operation will continue like before the shutdown. • Bit ...
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Bit 2 - PRUSART3: Power Reduction USART3 Writing a logic one to this bit shuts down the USART3 by stopping the clock to the module. When waking up the USART3 again, the USART3 should be re initialized to ensure ...
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System Control and Reset 12.1 Resetting the AVR During reset, all I/O Registers are set to their initial values, and the program starts execution from the Reset Vector. The instruction placed at the Reset Vector must be a JMP ...
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Figure 12-1. Reset Logic BODLEVEL [2..0] 12.2.1 Power-on Reset A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level is defined below the detection level. The POR circuit can be used to ...
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Figure 12-3. MCU Start-up, RESET Extended Externally TIME-OUT INTERNAL 12.2.2 External Reset An External Reset is generated by a low level on the RESET pin. Reset pulses longer than the minimum pulse width (see reset, even if the clock is ...
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Figure 12-5. Brown-out Reset During Operation 12.2.4 Watchdog Reset When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On the falling edge of this pulse, the delay timer starts counting the Time-out ...
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ADC is used. To reduce power consumption in Power-down mode, the user can avoid the three conditions above to ensure that the reference is turned off before entering Power-down mode. 12.4 Watchdog Timer 12.4.1 Features • Clocked from separate On-chip ...
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Watchdog set-up must follow timed sequences. The sequence for clearing WDE and changing time-out configuration is as follows the same operation, write a logic one to the Watchdog change enable bit (WDCE) and WDE. A ...
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Assembly Code Example WDT_off: C Code Example void WDT_off(void Note: The following code example shows one assembly and one C function for changing the time-out value of the Watchdog Timer. 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 (1) ; Turn off global ...
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Assembly Code Example WDT_Prescaler_Change: C Code Example void WDT_Prescaler_Change(void Notes: 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 (1) ; Turn off global interrupt cli ; Reset Watchdog Timer wdr ; Start timed sequence in r16, WDTCSR ori r16, (1<<WDCE) | (1<<WDE) out WDTCSR, ...
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Register Description 12.5.1 MCUSR – MCU Status Register The MCU Status Register provides information on which reset source caused an MCU reset. Bit 0x35 (0x55) Read/Write Initial Value • Bit 4 – JTRF: JTAG Reset Flag This bit is ...
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Bit 6 - WDIE: Watchdog Interrupt Enable When this bit is written to one and the I-bit in the Status Register is set, the Watchdog Interrupt is enabled. If WDE is cleared in combination with this setting, the Watchdog ...
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Table 12-2. WDP3 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 Watchdog Timer Prescale Select Number of WDT Oscillator WDP2 WDP1 WDP0 (2048) cycles 0 ...
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I/O-Ports 13.1 Introduction All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with ...
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Note that enabling the alternate function of some of the port pins does not affect the use of the other pins in the port as general digital I/O. 13.2 Ports as General Digital I/O The ports are bi-directional I/O ports ...
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If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven high (one). If PORTxn is written logic zero when the pin is configured as an output pin, the port pin ...
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Figure 13-3. Synchronization when Reading an Externally Applied Pin value INSTRUCTIONS Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is low, and goes transparent when the ...
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The following code example shows how to set port B pins 0 and 1 high, pins 2 and 3 low, and define the port pins from input with pull-ups assigned to port pins 6 and 7. ...
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Sleep mode, as the clamping in these sleep mode produces the requested logic change. 13.2.6 Unconnected Pins If some pins are unused recommended to ensure that these pins have a defined level. Even though most of ...
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Figure 13-5. Alternate Port Functions Pxn PUOExn: PUOVxn: DDOExn: DDOVxn: PVOExn: PVOVxn: DIEOExn: Pxn DIGITAL INPUT-ENABLE OVERRIDE ENABLE DIEOVxn: Pxn DIGITAL INPUT-ENABLE OVERRIDE VALUE SLEEP: PTOExn: Note: 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 (1) PUOExn PUOVxn 1 0 DDOExn DDOVxn 1 0 PVOExn PVOVxn ...
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Table 13-2 ure 13-5 on page 76 generated internally in the modules having the alternate function. Table 13-2. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV AIO The following subsections shortly describe the alternate functions for each ...
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Alternate Functions of Port A The Port A has an alternate function as the address low byte and data lines for the External Memory Interface. Table 13-3. Port Pin PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 Table 13-4 ...
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Table 13-5. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO 13.3.2 Alternate Functions of Port B The Port B pins with alternate functions are shown in Table 13-6. Port Pin PB7 PB6 PB5 PB4 PB3 PB2 ...
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PCINT7, Pin Change Interrupt source 7: The PB7 pin can serve as an external interrupt source. • OC1B/PCINT6, Bit 6 OC1B, Output Compare Match B output: The PB6 pin can serve as an external output for the Timer/Counter1 Output Compare ...
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Table 13-7 shown in MISO signal, while MOSI is divided into SPI MSTR OUTPUT and SPI SLAVE INPUT. PCINT0, Pin Change Interrupt source 0: The PB0 pin can serve as an external interrupt source. Table 13-7. Signal Name PUOE PUOV ...
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Alternate Functions of Port C The Port C alternate function is as follows: Table 13-9. Table 13-10 signals shown in Table 13-10. Overriding Signals for Alternate Functions in PC7:PC4 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV ...
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Table 13-11. Overriding Signals for Alternate Functions in PC3:PC0 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO 13.3.4 Alternate Functions of Port D The Port D pins with alternate functions are shown in Table 13-12. Port ...
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INT3/TXD1 – Port D, Bit 3 INT3, External Interrupt source 3: The PD3 pin can serve as an external interrupt source to the MCU. TXD1, Transmit Data (Data output pin for the USART1). When the USART1 Transmitter is enabled, ...
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Table 13-13. Overriding Signals for Alternate Functions PD7:PD4 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV Table 13-14. Overriding Signals for Alternate Functions in PD3:PD0 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV AIO Note: 2549N–AVR–05/11 ...
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Alternate Functions of Port E The Port E pins with alternate functions are shown in Table 13-15. Port E Pins Alternate Functions Port Pin PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 Note: • INT7/ICP3/CLKO – Port E, Bit ...
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INT4/OC3B – Port E, Bit 4 INT4, External Interrupt source 4: The PE4 pin can serve as an External Interrupt source. OC3B, Output Compare Match B output: The PE4 pin can serve as an External output for the Timer/Counter3 ...
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Table 13-16. Overriding Signals for Alternate Functions PE7:PE4 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO Table 13-17. Overriding Signals for Alternate Functions in PE3:PE0 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI ...
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Alternate Functions of Port F The Port F has an alternate function as analog input for the ADC as shown in some Port F pins are configured as outputs essential that these do not switch when a ...
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Table 13-19. Overriding Signals for Alternate Functions in PF7:PF4 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO Table 13-20. Overriding Signals for Alternate Functions in PF3:PF0 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV ...
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OC0B – Port G, Bit 5 OC0B, Output Compare match B output: The PG5 pin can serve as an external output for the TImer/Counter0 Output Compare. The pin has to be configured as an output (DDG5 set) to serve ...
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Table 13-23. Overriding Signals for Alternate Functions in PG3:PG0 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV AIO 13.3.8 Alternate Functions of Port H The Port H alternate pin configuration is as follows: Table 13-24. Port H ...
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OC4B – Port H, Bit 4 OC4B, Output Compare Match B output: The PH4 pin can serve as an external output for the Timer/Counter2 Output Compare B. The pin has to be configured as an output (DDH4 set) to ...
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Table 13-26. Overriding Signals for Alternate Functions in PH3:PH0 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV AIO 13.3.9 Alternate Functions of Port J The Port J alternate pin configuration is as follows: Table 13-27. Port J ...
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TXD3/PCINT10 - Port J, Bit 1 TXD3, USART3 Transmit pin. PCINT10, Pin Change Interrupt Source 10. The PJ1 pin can serve as External Interrupt Sources. • RXD3/PCINT9 - Port J, Bit 0 RXD3, USART3 Receive pin. Receive Data (Data ...
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Table 13-28. Overriding Signals for Alternate Functions in PJ7:PJ4 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO Table 13-29. Overriding Signals for Alternate Functions in PJ3:PJ0 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE ...
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Table 13-30. Port K Pins Alternate Functions (Continued) Port Pin • ADC15:8/PCINT23:16 – Port K, Bit 7:0 ADC15:8, Analog to Digital Converter, Channel PCINT23:16, Pin Change Interrupt Source 23:16. The PK7:0 pins can serve as External Inter- ...
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Table 13-32. Overriding Signals for Alternate Functions in PK3:PK0 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV 13.3.11 Alternate Functions of Port L The Port L alternate pin configuration is as follows: Table 13-33. Port L Pins ...
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T5 – Port L, Bit 2 T5, Timer/Counter5 counter source. • ICP5 – Port L, Bit 1 ICP5, Input Capture Pin 5: The PL1 pin can serve as an Input Capture pin for Timer/Counter5. • ICP4 – Port L, ...
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Register Description for I/O-Ports 13.4.1 MCUCR – MCU Control Register Bit 0x35 (0x55) Read/Write Initial Value • Bit 4 – PUD: Pull-up Disable When this bit is written to one, the I/O ports pull-up resistors are disabled even if ...
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PORTC – Port C Data Register Bit 0x08 (0x28) Read/Write Initial Value 13.4.9 DDRC – Port C Data Direction Register Bit 0x07 (0x27) Read/Write Initial Value 13.4.10 PINC– Port C Input Pins Address Bit 0x06 (0x26) Read/Write Initial Value ...
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PINE – Port E Input Pins Address Bit 0x0C (0x2C) Read/Write Initial Value 13.4.17 PORTF – Port F Data Register Bit 0x11 (0x31) Read/Write Initial Value 13.4.18 DDRF – Port F Data Direction Register Bit 0x10 (0x30) Read/Write Initial ...
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DDRH – Port H Data Direction Register Bit (0x101) Read/Write Initial Value 13.4.25 PINH – Port H Input Pins Address Bit (0x100) Read/Write Initial Value 13.4.26 PORTJ – Port J Data Register Bit (0x105) Read/Write Initial Value 13.4.27 DDRJ ...
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PORTL – Port L Data Register Bit (0x10B) Read/Write Initial Value 13.4.33 DDRL – Port L Data Direction Register Bit (0x10A) Read/Write Initial Value 13.4.34 PINL – Port L Input Pins Address Bit (0x109) Read/Write Initial Value 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 ...
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Interrupts ...
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Table 14-1. Vector No Notes: 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 Reset and Interrupt Vectors (Continued) ...
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Reset and Interrupt Vector placement Table 14-2 BOOTRST and IVSEL settings. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations. This is also the ...
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When the BOOTRST Fuse is unprogrammed, the ...
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When the BOOTRST Fuse is programmed and the Boot section size set to 8Kbytes, the most typical and general program setup for the Reset and Interrupt Vector Addresses is: Address Labels Code .org 0x0002 0x00002 0x00004 ... 0x00070 ; .org ...
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Assembly Code Example Move_interrupts: C Code Example void Move_interrupts(void) { uchar temp; } 14.4 Register Description 14.4.1 MCUCR – MCU Control Register Bit 0x35 (0x55) Read/Write Initial Value • Bit 1 – IVSEL: Interrupt Vector Select When the IVSEL bit ...
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Interrupts will automatically be disabled while this sequence is executed. Interrupts are disabled in the cycle IVCE is set, and they remain disabled until after the instruction following the write to IVSEL. If IVSEL is not written, interrupts remain disabled ...
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External Interrupts The External Interrupts are triggered by the INT7:0 pin or any of the PCINT23:0 pins. Observe that, if enabled, the interrupts will trigger even if the INT7:0 or PCINT23:0 pins are configured as outputs. This feature provides ...
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Figure 15-1. Normal pin change interrupt. PCINT(0) clk pcint_in_(n) pcint_setflag 15.2 Register Description 15.2.1 EICRA – External Interrupt Control Register A The External Interrupt Control Register A contains control bits for interrupt sense control. Bit (0x69) Read/Write Initial Value • ...
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Table 15-1. ISCn1 Note: Table 15-2. Symbol t INT 15.2.2 EICRB – External Interrupt Control Register B Bit (0x6A) Read/Write Initial Value • Bits 7:0 – ISC71, ISC70 - ISC41, ISC40: External Interrupt ...
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EIMSK – External Interrupt Mask Register Bit 0x1D (0x3D) Read/Write Initial Value • Bits 7:0 – INT7:0: External Interrupt Request Enable When an INT7:0 bit is written to one and the I-bit in the Status Register ...
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Bit 0 – PCIE0: Pin Change Interrupt Enable 0 When the PCIE0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin change interrupt 0 is enabled. Any change on any enabled PCINT7:0 ...
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Bit 7:0 – PCINT15:8: Pin Change Enable Mask 15:8 Each PCINT15:8-bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT15:8 is set and the PCIE1 bit in EIMSK is set, pin change interrupt is ...
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Timer/Counter0 with PWM 16.1 Features • Two Independent Output Compare Units • Double Buffered Output Compare Registers • Clear Timer on Compare Match (Auto Reload) • Glitch Free, Phase Correct Pulse Width Modulator (PWM) • Variable PWM Period ...
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The Timer/Counter is inactive when no clock source is selected. The output from the Clock Select logic is referred to as the timer clock (clk The double buffered Output Compare Registers (OCR0A and ...
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Signal description (internal signals): count direction clear clk top bottom Depending of the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clk selected by the Clock Select bits (CS02:0). When no clock source ...
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Figure 16-3. Output Compare Unit, Block Diagram The OCR0x Registers are double buffered when using any of the Pulse Width Modulation (PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the dou- ble buffering is ...
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Similarly, do not write the TCNT0 value equal to BOTTOM when the counter is down-counting. The setup of the OC0x should be performed before setting the Data Direction Register for the port pin to output. The easiest way of ...
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Compare Output Mode and Waveform Generation The Waveform Generator uses the COM0x1:0 bits differently in Normal, CTC, and PWM modes. For all modes, setting the COM0x1 tells the Waveform Generator that no action on the OC0x Register ...
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Figure 16-5. CTC Mode, Timing Diagram TCNTn OCn (Toggle) Period An interrupt can be generated each time the counter value reaches the TOP value by using the OCF0A Flag. If the interrupt is enabled, the interrupt handler routine can be ...
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The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT0 slopes represent Com- pare Matches between OCR0x and TCNT0. Figure 16-6. Fast PWM Mode, Timing Diagram TCNTn OCnx ...
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Phase Correct PWM Mode The phase correct PWM mode (WGM02 provides a high resolution phase correct PWM waveform generation option. The phase correct PWM mode is based on a dual-slope operation. The counter counts repeatedly ...
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OC0x Register at the Compare Match between OCR0x and TCNT0 when the counter increments, and setting (or clearing) the OC0x Register at Com- pare Match between OCR0x and TCNT0 when the counter decrements. The ...
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Figure 16-9. Timer/Counter Timing Diagram, with Prescaler (f clk clk (clk TCNTn TOVn Figure 16-10 mode and PWM mode, where OCR0A is TOP. Figure 16-10. Timer/Counter Timing Diagram, Setting of OCF0x, with Prescaler (f clk clk (clk TCNTn OCRnx OCFnx ...
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Register Description 16.9.1 TCCR0A – Timer/Counter Control Register A Bit 0x24 (0x44) Read/Write Initial Value • Bits 7:6 – COM0A1:0: Compare Match Output A Mode These bits control the Output Compare pin (OC0A) behavior. If one or both of ...
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Table 16-4. COM0A1 Note: • Bits 5:4 – COM0B1:0: Compare Match Output B Mode These bits control the Output Compare pin (OC0B) behavior. If one or both of the COM0B1:0 bits are set, the OC0B output ...
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Table 16-7 rect PWM mode. Table 16-7. COM0B1 Note: • Bits 3, 2 – Res: Reserved Bits These bits are reserved bits and will always read as zero. • Bits 1:0 – WGM01:0: Waveform Generation Mode ...
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TCCR0B – Timer/Counter Control Register B Bit 0x25 (0x45) Read/Write Initial Value • Bit 7 – FOC0A: Force Output Compare A The FOC0A bit is only active when the WGM bits specify a non-PWM mode. However, for ensuring compatibility ...
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Table 16-9. CS02 external pin modes are used for the Timer/Counter0, transitions on the T0 pin will clock the counter even if the pin is configured as an output. This feature ...
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TIMSK0 – Timer/Counter Interrupt Mask Register Bit (0x6E) Read/Write Initial Value • Bits 7:3, 0 – Res: Reserved Bits These bits are reserved bits and will always read as zero. • Bit 2 – OCIE0B: Timer/Counter Output Compare Match ...
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Bit 0 – TOV0: Timer/Counter0 Overflow Flag The bit TOV0 is set when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared by writing a logic one ...
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Timer/Counter (Timer/Counter and 5) 17.1 Features • True 16-bit Design (that is, allows 16-bit PWM) • Three independent Output Compare Units • Double Buffered Output Compare Registers • One Input Capture Unit • Input Capture ...
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Figure 17-1. 16-bit Timer/Counter Block Diagram Note: 17.2.1 Registers The Timer/Counter (TCNTn), Output Compare Registers (OCRnA/B/C), and Input Capture Reg- ister (ICRn) are all 16-bit registers. Special procedures must be followed when accessing the 16- bit registers. These procedures are ...
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See “Output Compare Units” on page 145. Match Flag (OCFnA/B/C) which can be used to generate an Output Compare interrupt request. The Input Capture Register can capture the Timer/Counter value at a given external (edge trig- gered) event on either ...
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Assembly Code Examples C Code Examples Note: The assembly code example returns the TCNTn value in the r17:r16 register pair important to notice that accessing 16-bit registers are atomic operations interrupt occurs between the two instructions ...
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Assembly Code Example TIM16_ReadTCNTn: C Code Example unsigned int TIM16_ReadTCNTn( void ) { } Note: The assembly code example returns the TCNTn value in the r17:r16 register pair. 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 (1) ; Save global interrupt flag in r18,SREG ; Disable ...
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The following code examples show how atomic write of the TCNTn Register contents. Writing any of the OCRnA/B/C or ICRn Registers can be done by using the same principle. Assembly Code Example TIM16_WriteTCNTn: C Code Example void ...
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Counter Unit The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional counter unit. Figure 17-2 Figure 17-2. Counter Unit Block Diagram Signal description (internal signals): Count Direction Clear clk TOP BOTTOM The 16-bit counter is mapped ...
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Input Capture Unit The Timer/Counter incorporates an input capture unit that can capture external events and give them a time-stamp indicating time of occurrence. The external signal indicating an event, or mul- tiple events, can be applied via the ...
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The ICRn Register can only be written when using a Waveform Generation mode that utilizes the ICRn Register for defining the counter’s TOP value. In these cases the Waveform Genera- tion mode (WGMn3:0) bits must be set before the TOP ...
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Register has been read. After a change of the edge, the Input Capture Flag (ICFn) must be cleared by software (writing a logical one to the I/O bit location). For measuring frequency only, the clearing of the ICFn Flag is ...
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The OCRnx Register is double buffered when using any of the twelve Pulse Width Modulation (PWM) modes. For the Normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double buffering synchronizes the update ...
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Compare Match Output Unit The Compare Output mode (COMnx1:0) bits have two functions. The Waveform Generator uses the COMnx1:0 bits for defining the Output Compare (OCnx) state at the next compare match. Secondly the COMnx1:0 bits control the OCnx ...
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PWM refer to page 160. A change of the COMnx1:0 bits state will have effect at the first compare match after the bits are written. ...
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Normal Mode The simplest mode of operation is the Normal mode (WGMn3:0 = 0). In this mode the counting direction is always up (incrementing), and no counter clear is performed. The counter simply overruns when it passes its maximum ...
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TCNTn, the counter will miss the compare match. The counter will then have to count to its max- imum value (0xFFFF) and wrap around starting at 0x0000 before the compare match can occur. In many cases this feature is not ...
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Figure 17-7. Fast PWM Mode, Timing Diagram TCNTn OCnx OCnx Period The Timer/Counter Overflow Flag (TOVn) is set each time the counter reaches TOP. In addition the OCnA or ICFn Flag is set at the same timer clock cycle as ...
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The PWM frequency for the output can be calculated by the following equation: The N variable represents the prescaler divider (1, 8, 64, 256, or 1024). The extreme values for the OCRnx Register represents special cases when generating a PWM ...
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Figure 17-8. Phase Correct PWM Mode, Timing Diagram TCNTn OCnx OCnx Period The Timer/Counter Overflow Flag (TOVn) is set each time the counter reaches BOTTOM. When either OCRnA or ICRn is used for defining the TOP value, the OCnA or ...
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The PWM frequency for the output when using phase correct PWM can be calculated by the following equation: The N variable represents the prescaler divider (1, 8, 64, 256, or 1024). The extreme values for the OCRnx ...
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Figure 17-9. Phase and Frequency Correct PWM Mode, Timing Diagram TCNTn OCnx OCnx Period The Timer/Counter Overflow Flag (TOVn) is set at the same timer clock cycle as the OCRnx Registers are updated with the double buffer value (at BOTTOM). ...
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The extreme values for the OCRnx Register represents special cases when generating a PWM waveform output in the phase correct PWM mode. If the OCRnx is set equal to BOTTOM the output will be continuously low and if set equal ...
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Figure 17-12 frequency correct PWM mode the OCRnx Register is updated at BOTTOM. The timing diagrams will be the same, but TOP should be replaced by BOTTOM, TOP-1 by BOTTOM+1 and so on. The same renaming applies for modes that ...
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Register Description 17.11.1 TCCR1A – Timer/Counter 1 Control Register A Bit (0x80) Read/Write Initial Value 17.11.2 TCCR3A – Timer/Counter 3 Control Register A Bit (0x90) Read/Write Initial Value 17.11.3 TCCR4A – Timer/Counter 4 Control Register A Bit (0xA0) Read/Write ...
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Bit 1:0 – WGMn1:0: Waveform Generation Mode Combined with the WGMn3:2 bits found in the TCCRnB Register, these bits control the counting sequence of the counter, the source for maximum (TOP) counter value, and what type of wave- form ...
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Table 17-5 correct and frequency correct PWM mode. Table 17-5. COMnA1 COMnB1 COMnC1 Note: 17.11.5 TCCR1B – Timer/Counter 1 Control Register B Bit (0x81) Read/Write Initial Value 17.11.6 TCCR3B – Timer/Counter 3 Control Register B Bit ...
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Bit 6 – ICESn: Input Capture Edge Select This bit selects which edge on the Input Capture Pin (ICPn) that is used to trigger a capture event. When the ICESn bit is written to zero, a falling (negative) edge ...
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TCCR3C – Timer/Counter 3 Control Register C Bit (0x92) Read/Write Initial Value 17.11.11 TCCR4C – Timer/Counter 4 Control Register C Bit (0xA2) Read/Write Initial Value 17.11.12 TCCR5C – Timer/Counter 5 Control Register C Bit (0x122) Read/Write Initial Value • ...
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TCNT4H and TCNT4L –Timer/Counter 4 Bit (0xA5) (0xA4) Read/Write Initial Value 17.11.16 TCNT5H and TCNT5L –Timer/Counter 5 Bit (0x125) (0x124) Read/Write Initial Value The two Timer/Counter I/O locations (TCNTnH and TCNTnL, combined TCNTn) give direct access, both for read ...
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OCR3AH and OCR3AL – Output Compare Register 3 A Bit (0x99) (0x98) Read/Write Initial Value 17.11.21 OCR3BH and OCR3BL – Output Compare Register 3 B Bit (0x9B) (0x9A) Read/Write Initial Value 17.11.22 OCR3CH and OCR3CL – Output Compare Register ...
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OCR5BH and OCR5BL – Output Compare Register 5 B Bit (0x12B) (0x12A) Read/Write Initial Value 17.11.28 OCR5CH and OCR5CL –Output Compare Register 5 C Bit (0x12D) (0x12C) Read/Write Initial Value The Output Compare Registers contain a 16-bit value that ...
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The Input Capture is updated with the counter (TCNTn) value each time an event occurs on the ICPn pin (or optionally on the Analog Comparator output for Timer/Counter1). The Input Capture can be used for defining the counter TOP value. ...
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Bit 1 – OCIEnA: Timer/Countern, Output Compare A Match Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Countern Output Compare A Match interrupt is enabled. ...
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Bit 2 – OCFnB: Timer/Counter1, Output Compare B Match Flag This flag is set in the timer clock cycle after the counter (TCNTn) value matches the Output Compare Register B (OCRnB). Note that a Forced Output Compare (FOCnB) strobe ...
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Timer/Counter and 5 Prescaler Timer/Counter and 5 share the same prescaler module, but the Timer/Counters can have different prescaler settings. The description below applies to all Timer/Counters used as ...
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The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles from an edge has been applied to the Tn pin to the counter is updated. Enabling and disabling of the clock input must be ...
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Bit 0 – PSRSYNC: Prescaler Reset for Synchronous Timer/Counters When this bit is one, Timer/Counter0, Timer/Counter1, Timer/Counter3, Timer/Counter4 and Timer/Counter5 prescaler will be Reset. This bit is normally cleared immediately by hardware, except if the TSM bit is set. ...
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Output Compare Modulator (OCM1C0A) 19.1 Overview The Output Compare Modulator (OCM) allows generation of waveforms modulated with a carrier frequency. The modulator uses the outputs from the Output Compare Unit C of the 16-bit Timer/Counter1 and the Output Compare ...
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When the modulator is enabled the type of modulation (logical AND or OR) can be selected by the PORTB7 Register. Note that the DDRB7 controls the direction of the port independent of the COMnx1:0 bit setting. 19.2.1 Timing example Figure ...
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Timer/Counter2 with PWM and Asynchronous Operation Timer/Counter2 is a general purpose, single channel, 8-bit Timer/Counter module. The main features are: • Single Channel Counter • Clear Timer on Compare Match (Auto Reload) • Glitch-free, Phase Correct Pulse Width ...
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Registers The Timer/Counter (TCNT2) and Output Compare Register (OCR2A and OCR2B) are 8-bit reg- isters. Interrupt request (abbreviated to Int.Req.) signals are all visible in the Timer Interrupt Flag Register (TIFR2). All interrupts are individually masked with the Timer ...
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Figure 20-2. Counter Unit Block Diagram Signal description (internal signals): count direction clear clk top bottom Depending on the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clk selected by the Clock Select ...
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Normal Mode The simplest mode of operation is the Normal mode (WGM22:0 = 0). In this mode the counting direction is always up (incrementing), and no counter clear is performed. The counter simply overruns when it passes its maximum ...
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The waveform generated will have a maximum frequency when OCR2A is set to zero (0x00). The waveform frequency is defined by the following clk_I/O equation: The N variable represents the ...
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COM2A1:0 bits). A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by set- ting OC2x to toggle ...
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The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches BOTTOM. The Interrupt Flag can be used to generate an interrupt each time the counter reaches the BOTTOM value. In phase correct PWM mode, the compare unit allows ...
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Figure 20-6. Output Compare Unit, Block Diagram The OCR2x Register is double buffered when using any of the Pulse Width Modulation (PWM) modes. For the Normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. ...
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The setup of the OC2x should be performed before setting the Data Direction Register for the port pin to output. The easiest way of setting the OC2x value is to use the Force Output Com- pare (FOC2x) strobe bit in ...
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Compare Output Mode and Waveform Generation The Waveform Generator uses the COM2x1:0 bits differently in normal, CTC, and PWM modes. For all modes, setting the COM2x1 tells the Waveform Generator that no action on the OC2x Register ...
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Figure 20-10 Figure 20-10. Timer/Counter Timing Diagram, Setting of OCF2A, with Prescaler (f (clk TCNTn OCRnx OCFnx Figure 20-11 Figure 20-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Pres- (clk TCNTn (CTC) OCRnx OCFnx 20.8 Asynchronous Operation ...
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The CPU main clock frequency must be more than four times the Oscillator frequency. • When writing to one of the registers TCNT2, OCR2x, or TCCR2x, the value is transferred to a temporary register, and latched after two positive ...
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During asynchronous operation, the synchronization of the Interrupt Flags for the asynchronous timer takes three processor cycles plus one timer cycle. The timer is therefore advanced by at least one before the processor can read the timer value causing ...
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Register Description 20.10.1 TCCR2A –Timer/Counter Control Register A Bit (0xB0) Read/Write Initial Value • Bits 7:6 – COM2A1:0: Compare Match Output A Mode These bits control the Output Compare pin (OC2A) behavior. If one or both of the COM2A1:0 ...
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Table 20-4. COM2A1 Note: • Bits 5:4 – COM2B1:0: Compare Match Output B Mode These bits control the Output Compare pin (OC2B) behavior. If one or both of the COM2B1:0 bits are set, the OC2B output ...
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Table 20-7 rect PWM mode. Table 20-7. COM2B1 Note: • Bits 3, 2 – Res: Reserved Bits These bits are reserved bits and will always read as zero. • Bits 1:0 – WGM21:0: Waveform Generation Mode ...
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TCCR2B – Timer/Counter Control Register B Bit (0xB1) Read/Write Initial Value • Bit 7 – FOC2A: Force Output Compare A The FOC2A bit is only active when the WGM bits specify a non-PWM mode. However, for ensuring compatibility with ...
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Table 20-9. CS22 external pin modes are used for the Timer/Counter0, transitions on the T0 pin will clock the counter even if the pin is configured as an output. This feature ...
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ASSR – Asynchronous Status Register Bit (0xB6) Read/Write Initial Value • Bit 6 – EXCLK: Enable External Clock Input When EXCLK is written to one, and asynchronous clock is selected, the external clock input buf- fer is enabled and ...
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The mechanisms for reading TCNT2, OCR2A, OCR2B, TCCR2A and TCCR2B are different. When reading TCNT2, the actual timer value is read. When reading OCR2A, OCR2B, TCCR2A and TCCR2B the value in the temporary storage register is read. 20.10.7 TIMSK2 – ...
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Bit 0 – TOV2: Timer/Counter2 Overflow Flag The TOV2 bit is set (one) when an overflow occurs in Timer/Counter2. TOV2 is cleared by hard- ware when executing the corresponding interrupt handling vector. Alternatively, TOV2 is cleared by writing a ...
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SPI – Serial Peripheral Interface The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the ATmega640/1280/1281/2560/2561 and peripheral devices or between several AVR devices. The ATmega640/1280/1281/2560/2561 SPI includes the following features: • Full-duplex, Three-wire Synchronous Data Transfer ...
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Master and Slave prepare the data to be sent in their respective shift Registers, and the Master generates the required clock pulses on the SCK line to interchange data. Data is always shifted from Master to Slave on the Master ...
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When the SPI is enabled, the data direction of the MOSI, MISO, SCK, and SS pins is overridden according to Functions” on page Table 21-1. Pin MOSI MISO SCK SS Note: The following code examples show how to initialize the ...
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Assembly Code Example SPI_MasterInit: SPI_MasterTransmit: Wait_Transmit: C Code Example void SPI_MasterInit(void void SPI_MasterTransmit(char cData Note: 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 (1) ; Set MOSI and SCK output, all others input r17,(1<<DD_MOSI)|(1<<DD_SCK) ldi out DDR_SPI,r17 ; Enable SPI, Master, set ...
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The following code examples show how to initialize the SPI as a Slave and how to perform a simple reception. Assembly Code Example SPI_SlaveInit: SPI_SlaveReceive: C Code Example void SPI_SlaveInit(void char SPI_SlaveReceive(void Note: 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 (1) ...
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SS Pin Functionality 21.1.1 Slave Mode When the SPI is configured as a Slave, the Slave Select (SS) pin is always input. When SS is held low, the SPI is activated, and MISO becomes an output if configured so ...