AT89LP3240 Atmel Corporation, AT89LP3240 Datasheet - Page 6

• Manufacturer Part Number: AT89LP3240
• Manufacturer: Atmel Corporation

Specifications of AT89LP3240

• Flash (kbytes): 32 Kbytes
• Max. Operating Frequency: 20 MHz
• Cpu: 8051-1C
• Max I/o Pins: 38
• Spi: 1
• Twi (i2c): 1
• Uart: 1
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 153.8
• Sram (kbytes): 4.25
• Eeprom (bytes): 8192
• Self Program Memory: IAP
• Operating Voltage (vcc): 2.4 to 3.6
• Timers: 3
• Isp: SPI/OCD
• Watchdog: Yes

Table 1-1.
2. Overview
6
TQFP
35
36
37
38
39
40
41
42
43
44
PLCC
AT89LP3240/6440
Pin Number
41
42
43
44
1
2
3
4
5
6
AT89LP3240/6440 Pin Description
PDIP
37
38
39
40
1
2
3
4
5
VQFN
The AT89LP3240/6440 is a low-power, high-performance CMOS 8-bit microcontroller with
32K/64K bytes of In-System Programmable Flash program memory and 8K bytes of Flash data
memory. The device is manufactured using Atmel
ogy and is compatible with the industry-standard 8051 instruction set. The AT89LP3240/6440 is
built around an enhanced CPU core that can fetch a single byte from memory every clock cycle.
In the classic 8051 architecture, each fetch requires 6 clock cycles, forcing instructions to exe-
cute in 12, 24 or 48 clock cycles. In the AT89LP3240/6440 CPU, standard instructions need only
1 to 4 clock cycles providing 6 to 12 times more throughput than the standard 8051. Seventy
percent of instructions need only as many clock cycles as they have bytes to execute, and most
of the remaining instructions require only one additional clock. The enhanced CPU core is capa-
ble of 20 MIPS throughput whereas the classic 8051 CPU can deliver only 4 MIPS at the same
current consumption. Conversely, at the same throughput as the classic 8051, the new CPU
core runs at a much lower speed and thereby greatly reducing power consumption and EMI.
The AT89LP3240/6440 provides the following standard features: 32K/64K bytes of In-System
Programmable Flash program memory, 8K bytes of Flash data memory, 4352 bytes of RAM, up
to 38 I/O lines, three 16-bit timer/counters, up to six PWM outputs, a programmable watchdog
timer, two analog comparators, a 10-bit ADC/DAC with 8 input channels, a full-duplex serial port,
a serial peripheral interface, a two-wire serial interface, an internal RC oscillator, on-chip crystal
oscillator, and a four-level, twelve-vector interrupt system. A block diagram is shown in
1.
35
36
37
38
39
40
41
42
43
44
Symbol
P0.2
P0.1
P0.0
VDD
VDD
P1.0
P1.1
P1.2
P1.3
P1.4
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
Description
P0.2: User-configurable I/O Port 0 bit 2.
AD2: External memory interface Address/Data bit 2.
ADC2: ADC analog input 2.
P0.1: User-configurable I/O Port 0 bit 1.
AD1: External memory interface Address/Data bit 1.
ADC1: ADC analog input 1.
P0.0: User-configurable I/O Port 0 bit 0.
AD0: External memory interface Address/Data bit 0.
ADC0: ADC analog input 0.
Supply Voltage
Supply Voltage
P1.0: User-configurable I/O Port 1 bit 0.
T2: Timer 2 External Input or Clock Output.
GPI0: General-purpose Interrupt input 0.
P1.1: User-configurable I/O Port 1 bit 1.
T2EX: Timer 2 External Capture/Reload Input.
GPI1: General-purpose Interrupt input 1
P1.2: User-configurable I/O Port 1 bit 2.
GPI2: General-purpose Interrupt input 2.
P1.3: User-configurable I/O Port 1 bit 3.
GPI3: General-purpose Interrupt input 3.
P1.4: User-configurable I/O Port 1 bit 4.
SS: SPI Slave-Select.
GPI6: General-purpose Interrupt input 4.
®
's high-density nonvolatile memory technol-
3706C–MICRO–2/11
Figure 2-