AT89LP3240 Atmel Corporation, AT89LP3240 Datasheet - Page 112

• Manufacturer Part Number: AT89LP3240
• Manufacturer: Atmel Corporation

Specifications of AT89LP3240

• Flash (kbytes): 32 Kbytes
• Max. Operating Frequency: 20 MHz
• Cpu: 8051-1C
• Max I/o Pins: 38
• Spi: 1
• Twi (i2c): 1
• Uart: 1
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 153.8
• Sram (kbytes): 4.25
• Eeprom (bytes): 8192
• Self Program Memory: IAP
• Operating Voltage (vcc): 2.4 to 3.6
• Timers: 3
• Isp: SPI/OCD
• Watchdog: Yes

18.4
Table 18-1.
Table 18-2.
Table 18-3.
112
TWCR Address = AAH
Not Bit Addressable
Symbol
TWEN
STA
STO
TWIF
AA
TWSR Address = ABH
Not Bit Addressable
Symbol
TWS
TWAR Address = ACH
Not Bit Addressable
Symbol
TWA
GC
Bit
Bit
Bit
6-0
7-0
Register Overview
AT89LP3240/6440
TWS7
TWA6
Function
Two-wire Serial Interface Enable. Set to enable the TWI. Clear to disable the TWI.
Start Flag. Set to send a START condition on the bus. Must be cleared by software.
Stop Flag. Set to send a STOP condition on the bus. Cleared automatically by hardware when the STOP occurs.
Two-wire Interface Interrupt Flag. Set by hardware when the TWI requests an interrupt. TWIF must be cleared by
software. While TWIF is set, the SCL low period is stretched. Note that clearing this flag starts the operation of the TWI,
so all accesses to the other TWI registers (TWAR, TWSR and TWDR) must be complete before clearing this flag.
Assert Acknowledge Flag. Clear in master and slave receiver modes, to force a not acknowledge (high level on SDA).
Clear to disable SLA or GCA recognition. Set to recognize SLA or GCA (if GC set) for entering slave receiver or
transmitter modes. Set in master and slave receiver modes, to force an acknowledge (low level on SDA). This bit has no
effect when in master transmitter mode. By clearing AA to zero, the device can be virtually disconnected from the Two-
wire Serial Bus temporarily. Address recognition can then be resumed by setting the AA bit to one again.
Function
Two-wire Interface Status. The current status code of the TWI logic and serial bus. See
for a description of the status codes. Note that the three least significant bits always read as zero. The Status code is
valid only while TWIF remains set.
Function
Two-wire Interface Slave Address. The TWI will only respond to slave addresses that match this 7-bit address.
General Call Enable. Set to enable General Call address (00h) recognition. Clear to disable General Call address
recognition.
–
7
7
7
TWCR – Two-Wire Control Register
TWSR – Two-Wire Status Register
TWAR – Two-Wire Address Register
TWEN
TWS6
TWA5
6
6
6
TWS5
TWA4
STA
5
5
5
TWS4
TWA3
STO
4
4
4
TWS3
TWA2
TWIF
3
3
3
TWA1
AA
2
0
2
2
Reset Value = X000 00XXB
Reset Value = 1111 1000B
Reset Value = 1111 1110B
Table 18-6
TWA0
–
1
0
1
1
through
GC
3706C–MICRO–2/11
–
0
0
0
0
Table 18-10