AT89LP3240 Atmel Corporation, AT89LP3240 Datasheet - Page 155

• Manufacturer Part Number: AT89LP3240
• Manufacturer: Atmel Corporation

Specifications of AT89LP3240

• Flash (kbytes): 32 Kbytes
• Max. Operating Frequency: 20 MHz
• Cpu: 8051-1C
• Max I/o Pins: 38
• Spi: 1
• Twi (i2c): 1
• Uart: 1
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 153.8
• Sram (kbytes): 4.25
• Eeprom (bytes): 8192
• Self Program Memory: IAP
• Operating Voltage (vcc): 2.4 to 3.6
• Timers: 3
• Isp: SPI/OCD
• Watchdog: Yes

24. On-Chip Debug System
24.1
3706C–MICRO–2/11
Physical Interface
Table 23-1.
The AT89LP3240/6440 On-Chip Debug (OCD) System uses a two-wire serial interface to con-
trol program flow; read, modify, and write the system state; and program the nonvolatile
memory. The OCD System has the following features:
The On-Chip Debug System uses a two-wire synchronous serial interface to establish communi-
cation between the target device and the controlling emulator system. The OCD interface is
enabled by clearing the OCD Enable Fuse. The OCD device connections are shown in
24-1. When OCD is enabled, the RST port pin is configured as an input for the Debug Clock
(DCL). Either the XTAL1, XTAL2 or P4.3 pin is configured as a bi-directional data line for the
Debug Data (DDA) depending on the clock source selected. If the Internal RC Oscillator is
selected, XTAL1 is configured as DDA (A).If the External Clock is selected, XTAL2 is configured
as DDA (B). If the Crystal Oscillator is selected, P4.3 is configured as DDA (C).
When designing a system where On-Chip Debug will be used, the following observations must
be considered for correct operation:
TH0
TH1
TH2
TL0
TL1
TL2
TMOD
TWAR
TWBR
TWCR
TWDR
TWSR
WDTCON
WDTRST
• Complete program flow control
• Read-Modify-Write access to all internal SFRs and data memories
• Four hardware program address breakpoints, plus four program/data address breakpoints
• Unlimited program software breakpoints using BREAK instruction
• Break on change in program memory flow
• Break on stack overflow/underflow
• Break on Watchdog overflow
• Break on reset
• Non-intrusive operation
• Programming of nonvolatile memory
Special Function Register Cross Reference
8CH
8DH
CDH
8AH
8BH
CCH
89H
ACH
AEH
AAH
ADH
ABH
A7H
A6H
Table 11-1 on page 51
Table 11-1 on page 51
Section 12.1 on page 61
Table 11-1 on page 51
Table 11-1 on page 51
Section 12.1 on page 61
Table 11-3 on page 55
Table 18-3 on page 112
Table 18-5 on page 113
Table 18-1 on page 112
Table 18-4 on page 113
Table 18-2 on page 112
Table 21-2 on page 142
Table 21-3 on page 142
AT89LP3240/6440
Figure
155