AT89C51IC2 Atmel Corporation, AT89C51IC2 Datasheet - Page 13
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AT89C51IC2
Manufacturer Part Number
AT89C51IC2
Description
Manufacturer
Atmel Corporation
Specifications of AT89C51IC2
Flash (kbytes)
32 Kbytes
Max. Operating Frequency
60 MHz
Cpu
8051-12C
Max I/o Pins
34
Spi
1
Twi (i2c)
1
Uart
1
Sram (kbytes)
1.25
Self Program Memory
API
Operating Voltage (vcc)
2.7 to 5.5
Timers
4
Isp
UART
Watchdog
Yes
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Quantity
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Table 13. Pin Description for 40/44 Pin Packages (Continued)
4301D–8051–02/08
RST
ALE/PROG
PSEN
EA
Mnemonic
PLCC44
10
33
32
35
Pin Number
VQFP44 1.4
27
26
29
4
Type
O (I)
I/O
O
I
Name and Function
SDA is the bidirectional 2-wire data line
Reset: A high on this pin for two machine cycles while the oscillator is running, resets
the device. An internal diffused resistor to V
external capacitor to V
system reset.
Address Latch Enable/Program Pulse: Output pulse for latching the low byte of the
address during an access to external memory. In normal operation, ALE is emitted at a
constant rate of 1/6 (1/3 in X2 mode) the oscillator frequency, and can be used for
external timing or clocking. Note that one ALE pulse is skipped during each access to
external data memory. This pin is also the program pulse input (PROG) during Flash
programming. ALE can be disabled by setting SFR’s AUXR.0 bit. With this bit set, ALE
will be inactive during internal fetches.
Program Strobe ENable: The read strobe to external program memory. When execut-
ing code from the external program memory, PSEN is activated twice each machine
cycle, except that two PSEN activations are skipped during each access to external
data memory. PSEN is not activated during fetches from internal program memory.
External Access Enable: EA must be externally held low to enable the device to fetch
code from external program memory locations 0000H to FFFFH (RD). If security level 1
is programmed, EA will be internally latched on Reset.
CC
. This pin is an output when the hardware watchdog forces a
SS
permits a power-on reset using only an
13