AT32UC3C1128C Atmel Corporation, AT32UC3C1128C Datasheet - Page 989
AT32UC3C1128C
Manufacturer Part Number
AT32UC3C1128C
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(159 pages)
3.AT32UC3C0128C.pdf
(1313 pages)
4.AT32UC3C0128C.pdf
(108 pages)
Specifications of AT32UC3C1128C
Flash (kbytes)
128 Kbytes
Pin Count
100
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
Hardware Qtouch Acquisition
No
Max I/o Pins
81
Ext Interrupts
100
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
7
Twi (i2c)
3
Uart
5
Can
2
Lin
5
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
4
Dac Resolution (bits)
12
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
36
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6 or 4.5 to 5.5
Operating Voltage (vcc)
3.0 to 3.6 or 4.5 to 5.5
Fpu
Yes
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
22
Input Capture Channels
12
Pwm Channels
19
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3C1128C-AUR
Manufacturer:
ATMEL
Quantity:
870
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33.6.5
33.6.5.1
32117C–AVR-08/11
PWM Controller Operations
Initialization
Before enabling the channels, they must have been configured by the software application:
• Unlock user interface by writing the WPCMD field in the WPCR Register.
• Configuration of the clock generator (DIVA, PREA, DIVB, PREB, CLKSEL in the CLK register
• Selection of the clock for each channel (CPRE field in the CMRx register)
• Configuration of the waveform alignment for each channel (CALG field in the CMRx register)
• Selection of the counter event selection (if CALG=1) for each channel (CES field in the CMRx
• Configuration of the output waveform polarity for each channel (CPOL in the CMRx register)
• Configuration of the period for each channel (CPRD in the CPRDx register). Writing in
• Configuration of the duty-cycle for each channel (CDTY in the CDTYx register). Writing in
• Configuration of the dead-time generator for each channel (DTH and DTL in DTx) if enabled
• Selection of the synchronous channels (SYNCx in the SCM register)
• Selection of the moment when the WRDY bit and the corresponding PDCA transfer request
• Configuration of the update mode (UPDM in the SCM register)
• Configuration of the update period (UPR in the SCUP register) if needed.
• Configuration of the comparisons (CMPxV and CMPxM).
• Configuration of the event lines (ELxMR).
• Configuration of the fault inputs polarity (FPOL in FMR)
• Configuration of the fault protection (FMOD and FFIL in FMR, FPV and FPE1)
• Enable of the interrupts (writing CHIDx and FCHIDx in IER1 register, and writing WRDYE,
• Enable of the channels (writing CHIDx in the ENA register)
if required). After writing CLKSEL to a new value, no write in any PWM registers must be
attempted before a delay of 2 master clock periods (CLK_PWM). This is the time needed by
the PWM to switch the internal clock (CCK).
register)
CPRDx register is possible while the channel is disabled. After validation of the channel, the
user must use CPRDUPDx register to update CPRDx as explained below.
CDTYx register is possible while the channel is disabled. After validation of the channel, the
user must use CDTYUPDx register to update CDTYx as explained below.
(DTE bit in the CMRx register). Writing in the DTx register is possible while the channel is
disabled. After validation of the channel, the user must use DTUPDx register to update DTx
are set (PTRM and PTRCS in the SCM register)
UNRE, CMPMx and CMPUx in IER2 register)
AT32UC3C
989
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