AT32UC3C1128C Atmel Corporation, AT32UC3C1128C Datasheet - Page 1112
AT32UC3C1128C
Manufacturer Part Number
AT32UC3C1128C
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(159 pages)
3.AT32UC3C0128C.pdf
(1313 pages)
4.AT32UC3C0128C.pdf
(108 pages)
Specifications of AT32UC3C1128C
Flash (kbytes)
128 Kbytes
Pin Count
100
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
Hardware Qtouch Acquisition
No
Max I/o Pins
81
Ext Interrupts
100
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
7
Twi (i2c)
3
Uart
5
Can
2
Lin
5
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
4
Dac Resolution (bits)
12
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
36
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6 or 4.5 to 5.5
Operating Voltage (vcc)
3.0 to 3.6 or 4.5 to 5.5
Fpu
Yes
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
22
Input Capture Channels
12
Pwm Channels
19
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3C1128C-AUR
Manufacturer:
ATMEL
Quantity:
870
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36.6.8.1
36.6.8.2
32117C–AVR-08/11
Dynamic mode
Gain factor
Dynamic mode aims at improving conversion accuracy when performing channel sweeping or
measures on high frequency input signals. It is then recommended using the SHDYN (sample
and hold dynamic mode) bit control in the SEQCFGx register. Doing this causes the insertion of
a supplementary sampling cycle of one CkADC clock period used to reset the sample and hold.
As a consequence, conversion rate is divided by two. Please note that it is useless performing
oversampling when using that mode since the S/H are reseted before actually sampling.
Figure 36-9. SH Dynamic Mode
S/H allows the amplification of very small signals or buffering of very high impedance signal
sources. The gain factor may be configured from 1x to 64x by writing to the Sequencer Conver-
sion n Sample and Hold Gain (GCNVn) field of the SHGx register. The gain can be changed
from sample to sample by writing the SHGx registers.
Table 36-7.
0
0
0
0
1
1
1
1
GCNVn
0
0
1
1
0
0
1
1
Gain Factor
0
1
0
1
0
1
0
1
Gain
1
2
4
8
16
32
64
Reserved
AT32UC3C
1112
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