AT32UC3C1128C Atmel Corporation, AT32UC3C1128C Datasheet - Page 437
AT32UC3C1128C
Manufacturer Part Number
AT32UC3C1128C
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(159 pages)
3.AT32UC3C0128C.pdf
(1313 pages)
4.AT32UC3C0128C.pdf
(108 pages)
Specifications of AT32UC3C1128C
Flash (kbytes)
128 Kbytes
Pin Count
100
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
Hardware Qtouch Acquisition
No
Max I/o Pins
81
Ext Interrupts
100
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
7
Twi (i2c)
3
Uart
5
Can
2
Lin
5
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
4
Dac Resolution (bits)
12
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
36
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6 or 4.5 to 5.5
Operating Voltage (vcc)
3.0 to 3.6 or 4.5 to 5.5
Fpu
Yes
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
22
Input Capture Channels
12
Pwm Channels
19
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3C1128C-AUR
Manufacturer:
ATMEL
Quantity:
870
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22.6
The following addresses are used by SAU channel configuration registers. All offsets are relative to the SAU’s PB base
address.
Table 22-1.
Note:
The following addresses are used by SAU channel registers. All offsets are relative to the SAU’s HSB base address. The
number of channels implemented is device specific, refer to the Module Configuration section at the end of this chapter.
Table 22-2.
32117C–AVR-08/11
0x04*n
Offset
Offset
0x0C
0x1C
0xFC
0x00
0x04
0x08
0x10
0x14
0x18
0x20
0x24
0x28
0x00
0x04
0x08
...
User Interface
1.
The reset values are device specific. Please refer to the Module Configuration section at the
SAU Configuration Register Memory Map
SAU Channel Register Memory Map
Channel Enable Register High
Channel Enable Register Low
Interrupt Disable Register
Remap Target Register 0
Remap Target Register 1
Remap Target Register 2
Remap Target Register n
Interrupt Enable Register
Interrupt Mask Register
Interrupt Clear Register
Configuration Register
Parameter Register
Control Register
Version Register
Unlock Register
Status Register
Register
Register
...
Register Name
Register Name
PARAMETER
VERSION
CONFIG
CERH
RTR0
RTR1
RTR2
RTRn
CERL
IMR
IER
IDR
ICR
UR
CR
SR
...
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read-only
Read-only
Read-only
Write-only
Write-only
Write-only
Write-only
Write-only
Write-only
Read-only
Access
Access
...
AT32UC3C
end of this chapter.
0x00000000
0x00000000
0x00000000
0x00000000
0x00000400
0x00000000
0x00000000
0x00000000
0x00000000
Reset
Reset
N/A
N/A
N/A
N/A
N/A
-
-
...
(1)
(1)
437
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