AT32UC3C1128C Atmel Corporation, AT32UC3C1128C Datasheet - Page 416
AT32UC3C1128C
Manufacturer Part Number
AT32UC3C1128C
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(159 pages)
3.AT32UC3C0128C.pdf
(1313 pages)
4.AT32UC3C0128C.pdf
(108 pages)
Specifications of AT32UC3C1128C
Flash (kbytes)
128 Kbytes
Pin Count
100
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
Hardware Qtouch Acquisition
No
Max I/o Pins
81
Ext Interrupts
100
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
7
Twi (i2c)
3
Uart
5
Can
2
Lin
5
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
4
Dac Resolution (bits)
12
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
36
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6 or 4.5 to 5.5
Operating Voltage (vcc)
3.0 to 3.6 or 4.5 to 5.5
Fpu
Yes
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
22
Input Capture Channels
12
Pwm Channels
19
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3C1128C-AUR
Manufacturer:
ATMEL
Quantity:
870
- AT32UC3A0128 PDF datasheet
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- AT32UC3C0128C PDF datasheet #3
- AT32UC3C0128C PDF datasheet #4
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21.7.1
Name:
Access Type :
Offset:
Reset Value:
• ARB: Arbitration Mode
• CHxDIS: Channel Disable
• CHxM: Channel Mode
• CHxEN: Channel Enable
32117C–AVR-08/11
31
23
15
7
-
-
-
-
0: The MDMA is in Fixed Priority Mode.
1: The MDMA is in Round-Robin Mode.
Writing a zero to this bit has no effect.
Writing a one to this bit disables the MDMA channel after the current transfer has completed.
To avoid hazards, CHxDIS bits can only be changed by writing a value to CR where the corresponding CHxEN bit is set.
This bit is automatically cleared by hardware when the corresponding channel has been disabled.
0: The channel is in Single Transfer Mode.
1: The channel is in Descriptor Mode.
To avoid hazards, CHxM bits can only be changed by writing a value to CR where the corresponding CHxEN bit is set.
Writing a zero to this bit this bit has no effect.
Writing a one to this bit enables the channel for DMA transfer.
This bit is automatically cleared if the transfer completes when the channel is in single transfer mode.
This bit is automatically cleared if the transfer completes when the channel is in descriptor mode, and the next descriptor read in
has a cleared Valid bit.
This bit is automatically cleared when the corresponding channel has been disabled by writing a one to CHxDIS.
Control Register
30
22
14
6
-
-
-
-
CR
Read/Write
0x00
0x000000000
29
21
13
5
-
-
-
-
28
20
12
4
-
-
-
-
CH3DIS
CH3EN
CH3M
27
19
11
3
-
CH2DIS
CH2EN
CH2M
26
18
10
2
-
CH1DIS
CH1EN
CH1M
25
17
9
1
-
AT32UC3C
CH0DIS
CH0EN
CH0M
ARB
24
16
8
0
416
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