AT32UC3C1128C Atmel Corporation, AT32UC3C1128C Datasheet - Page 636
AT32UC3C1128C
Manufacturer Part Number
AT32UC3C1128C
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(159 pages)
3.AT32UC3C0128C.pdf
(1313 pages)
4.AT32UC3C0128C.pdf
(108 pages)
Specifications of AT32UC3C1128C
Flash (kbytes)
128 Kbytes
Pin Count
100
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
Hardware Qtouch Acquisition
No
Max I/o Pins
81
Ext Interrupts
100
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
7
Twi (i2c)
3
Uart
5
Can
2
Lin
5
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
4
Dac Resolution (bits)
12
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
36
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6 or 4.5 to 5.5
Operating Voltage (vcc)
3.0 to 3.6 or 4.5 to 5.5
Fpu
Yes
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
22
Input Capture Channels
12
Pwm Channels
19
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3C1128C-AUR
Manufacturer:
ATMEL
Quantity:
870
- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- AT32UC3C0128C PDF datasheet #3
- AT32UC3C0128C PDF datasheet #4
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- Download datasheet (20Mb)
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32117C–AVR-08/11
FRAME: Framing Error
OVRE: Overrun Error
RXBRK: Break Received/End of Break
TXRDY: Transmitter Ready
RXRDY: Receiver Ready
0: No parity error has been detected since the last RSTSTA.
1: At least one parity error has been detected since the last RSTSTA.
0: No stop bit has been detected low since the last RSTSTA.
1: At least one stop bit has been detected low since the last RSTSTA.
0: No overrun error has occurred since the last RSTSTA.
1: At least one overrun error has occurred since the last RSTSTA.
0: No Break received or End of Break detected since the last RSTSTA.
1: Break Received or End of Break detected since the last RSTSTA.
0: A character is in the THR waiting to be transferred to the Transmit Shift Register, or an STTBRK command has been
1: There is no character in the THR.
0: No complete character has been received since the last read of RHR or the receiver is disabled. If characters were being
1: At least one complete character has been received and RHR has not yet been read.
requested, or the transmitter is disabled. As soon as the transmitter is enabled, TXRDY becomes 1.
received when the receiver was disabled, RXRDY changes to 1 when the receiver is enabled.
AT32UC3C
636
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