AT32UC3C0256C Atmel Corporation, AT32UC3C0256C Datasheet - Page 705

• Manufacturer Part Number: AT32UC3C0256C
• Manufacturer: Atmel Corporation

Specifications of AT32UC3C0256C

• Flash (kbytes): 256 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 123
• Ext Interrupts: 144
• Usb Transceiver: 1
• Quadrature Decoder Channels: 2
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 7
• Twi (i2c): 3
• Uart: 5
• Can: 2
• Lin: 5
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 4
• Dac Resolution (bits): 12
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 68
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6 or 4.5 to 5.5
• Operating Voltage (vcc): 3.0 to 3.6 or 4.5 to 5.5
• Fpu: Yes
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 22
• Input Capture Channels: 12
• Pwm Channels: 20
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

Figure 27-9. Master Read with Multiple Data Bytes
27.8.5
27.8.5.1
32117C–AVR-08/11
SR.IDLE
RXRDY
TWD
Using the Peripheral DMA Controller
NBYTES set to m
Write START +
Data Transmit with the Peripheral DMA Controller
S
STOP bit
DADR
Writing CMDR with START=STOP=1 and NBYTES=0 will generate a transmission with no data
bytes, ie START, DADR+R, STOP
The TWI transfers require the master to acknowledge each received data byte. During the
acknowledge clock pulse (9th pulse), the slave releases the data line (HIGH), enabling the mas-
ter to pull it down in order to generate the acknowledge. All data bytes except the last are
acknowledged by the master. Not acknowledging the last byte informs the slave that the transfer
is finished.
RXRDY is used as Receive Ready for the Peripheral DMA Controller receive channel.
Figure 27-8. Master Read with One Data Byte
The use of the Peripheral DMA Controller significantly reduces the CPU load. The user can set
up ring buffers for the Peripheral DMA Controller, containing data to transmit or free buffer space
to place received data.
To assure correct behavior, respect the following programming sequences:
SR.IDLE
5. Decrement NBYTES
6. If (NBYTES==0) and STOP=1, transmit STOP condition.
1. Initialize the transmit Peripheral DMA Controller (memory pointers, size, etc.).
2. Configure the TWIM (ADR, NBYTES, etc.).
RXRDY
TWD
R
NBYTES set to 1
Write START &
S
STOP bit
A
DADR
DATAn
R
Read RHR
DATAn
A
A
DATAn+1
DATA
DATAn+m-2
Read RHR
DATAn+m-1
N
Read RHR
P
DATAn+m-1
Read RHR
A
DATAn+m
When NBYTES=0
Send STOP
AT32UC3C
N
Read RHR
DATAn+m
P
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