AT32UC3C0256C Atmel Corporation, AT32UC3C0256C Datasheet - Page 51
AT32UC3C0256C
Manufacturer Part Number
AT32UC3C0256C
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(159 pages)
3.AT32UC3C0128C.pdf
(1313 pages)
4.AT32UC3C0128C.pdf
(108 pages)
Specifications of AT32UC3C0256C
Flash (kbytes)
256 Kbytes
Pin Count
144
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
Hardware Qtouch Acquisition
No
Max I/o Pins
123
Ext Interrupts
144
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
7
Twi (i2c)
3
Uart
5
Can
2
Lin
5
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
4
Dac Resolution (bits)
12
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
68
Self Program Memory
YES
External Bus Interface
1
Dram Memory
sdram
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6 or 4.5 to 5.5
Operating Voltage (vcc)
3.0 to 3.6 or 4.5 to 5.5
Fpu
Yes
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
22
Input Capture Channels
12
Pwm Channels
20
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- AT32UC3C0128C PDF datasheet #3
- AT32UC3C0128C PDF datasheet #4
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- Download datasheet (20Mb)
7.3
Figure 7-1.
7.4
Table 7-1.
7.5
7.5.1
7.5.2
32117C–AVR-08/11
Name
RESET_N
Block Diagram
I/O Lines Description
Product Dependencies
Interrupt
Clock Implementation
External Reset Pin
PM Block Diagram
I/O Lines Description
Power-On
Detector
The PM interrupt line is connected to one of the internal sources of the interrupt controller. Using
the PM interrupt requires the interrupt controller to be programmed first.
In AT32UC3C, the HSB shares the source clock with the CPU. This means that writing to the
HSBSEL register has no effect. This register will always read the same value as CPUSEL.
The clock for the PM bus interface (CLK_PM) is generated by the Power Manager. This clock is
enabled at reset, and can be disabled in the Power Manager, whoever if disabled it can only be
re-enabled by a reset.
Main Clock Sources
Description
Reset
Reset Sources
Interrupts
Clock Generator
Reset Controller
Sleep Controller
Type
Input
Synchronous
Synchronous
CPU, HSB,
Instruction
Active Level
Low
Resets
clocks
Sleep
PBx
AT32UC3C
51
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